Silicon Issue Summary
Module | Feature | Item No. | Issue Summary | Affected Revisions | ||||||
---|---|---|---|---|---|---|---|---|---|---|
A2 | A3 | A5 | A6 | A7 | A8 | A9 | ||||
Data EE Memory | Memory Endurance | 1.1.1 | Erase/Write Endurance Limited | X | X | X | ||||
Writes | 1.1.2 | Minimum VDD for Writes | X | X | X | X | X | X | X | |
Program Flash Memory (PFM) | Memory Endurance | 1.2.1 | Erase/Write Endurance Limited | X | X | X | ||||
Writes | 1.2.2 | Minimum VDD for Writes | X | X | X | X | X | X | X | |
Capture Compare PWM (CCP) | PWM Dead-Band Delay | 1.3.1 | Dead-Band Delay Results in Unpredictable Waveforms | X | X | X | X | X | X | X |
ECCP2 Switching | 1.3.2 | ECCP2 Switching Between Single, Half-Bridge, and Full-Bridge PWM Modes | X | X | X | X | X | X | X | |
ECCP2 Changing Direction | 1.3.3 | ECCP2 PWM Outputs Will Improperly Go Active | X | X | X | X | X | X | X | |
Capture Mode | 1.3.4 | Capture Triggered While CCPx Pin is Held High | X | X | X | X | X | X | X | |
ECCPx Dead-Band Delay | 1.3.5 | ECCPx Dead-Band Delay in Half-Bridge Mode | X | X | X | X | X | X | X | |
PWM with Pulse Steering | 1.3.6 | Disabling a PWM Output During a PWM Cycle May Stop the Output Earlier than Expected | X | X | X | X | X | X | X | |
Capture Mode | 1.3.7 | Capture Triggered While CCPx Pin is Held Low | X | X | X | X | X | X | X | |
Brown-Out Reset (BOR) | Threshold | 1.4.1 | BOR Threshold Voltage Level | X | ||||||
Analog-to-Digital Converter (ADC) | ADC Conversion | 1.5.1 | ADC Conversion May Not Complete | X | X | X | ||||
Oscillator (OSC) | HS Oscillator | 1.6.1 | HS Oscillator Minimum VDD | X | X | X | ||||
Oscillator Start-Up Timer (OSTS) Bit | 1.6.2 | OSTS Bit Remains Set | X | X | X | X | X | X | ||
MFINTOSC | 1.6.3 | The Device May not Wake from Sleep when Using the MF Internal Oscillator | X | X | X | X | X | X | X | |
Enhanced Capture Compare PWM (ECCP) | Enhanced PWM | 1.7.1 | PWM 0% Duty Cycle Direction Change | X | X | X | X | X | X | X |
Enhanced PWM | 1.7.2 | PWM 0% Duty Cycle Port Steering | X | X | X | X | X | X | X | |
Timer1 | Timer0 Gate Source | 1.8.1 | Gate Toggle Mode Works Improperly | X | X | X | X | X | X | X |
Timer1 Gate Toggle Mode | 1.8.2 | T1 Gate Flip-Flop Does Not Clear | X | X | X | X | X | X | X | |
LDO | Minimum VDD above 85°C | 1.9.1 | Minimum Operating VDD for the PIC16F193x devices at TA > 85°C | X | X | X | X | X | X | X |
Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) | Auto-Baud Detect | 1.10.1 | Auto-Baud Detect May Store Incorrect Count Value in the SPBRG Registers | X | X | X | X | X | ||
Resets | RESET Instruction | 1.11.1 | Extended Reset if Clock is MFINTOSC or HFINTOSC | X | X | X | X | X | X | |
Master Synchronous Serial Port (MSSP) | SPI Master Mode | 1.12.1 | The Buffer Full (BF) Bit or MSSP Interrupt Flag (SSPIF) Bit Becomes Set Half of a SCK Cycle Early | X | X | X | X | X | X | X |
Note: Only those issues indicated in the last column
apply to the current silicon revision.
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