Silicon Issue Summary

Table . Silicon Issue Summary
ModuleFeatureItem No.Issue SummaryAffected Revisions
A2A3A5A6A7A8A9
Data EE MemoryMemory Endurance1.1.1Erase/Write Endurance LimitedXXX
Writes1.1.2Minimum VDD for WritesXXXXXXX
Program Flash Memory (PFM)Memory Endurance1.2.1Erase/Write Endurance LimitedXXX
Writes1.2.2Minimum VDD for WritesXXXXXXX
Capture Compare PWM (CCP)PWM Dead-Band Delay1.3.1Dead-Band Delay Results in Unpredictable WaveformsXXXXXXX
ECCP2 Switching1.3.2ECCP2 Switching Between Single, Half-Bridge, and Full-Bridge PWM ModesXXXXXXX
ECCP2 Changing Direction1.3.3ECCP2 PWM Outputs Will Improperly Go ActiveXXXXXXX
Capture Mode1.3.4Capture Triggered While CCPx Pin is Held HighXXXXXXX
ECCPx Dead-Band Delay1.3.5ECCPx Dead-Band Delay in Half-Bridge ModeXXXXXXX
PWM with Pulse Steering1.3.6Disabling a PWM Output During a PWM Cycle May Stop the Output Earlier than ExpectedXXXXXXX
Capture Mode1.3.7Capture Triggered While CCPx Pin is Held LowXXXXXXX
Brown-Out Reset (BOR)Threshold1.4.1BOR Threshold Voltage LevelX
Analog-to-Digital Converter (ADC)ADC Conversion1.5.1ADC Conversion May Not CompleteXXX
Oscillator (OSC)HS Oscillator1.6.1HS Oscillator Minimum VDDXXX
Oscillator Start-Up Timer (OSTS) Bit1.6.2OSTS Bit Remains SetXXXXXX
MFINTOSC1.6.3The Device May not Wake from Sleep when Using the MF Internal OscillatorXXXXXXX
Enhanced Capture Compare PWM (ECCP)Enhanced PWM1.7.1PWM 0% Duty Cycle Direction ChangeXXXXXXX
Enhanced PWM1.7.2PWM 0% Duty Cycle Port SteeringXXXXXXX
Timer1Timer0 Gate Source1.8.1Gate Toggle Mode Works ImproperlyXXXXXXX
Timer1 Gate Toggle Mode1.8.2T1 Gate Flip-Flop Does Not ClearXXXXXXX
LDOMinimum VDD above 85°C1.9.1Minimum Operating VDD for the PIC16F193x devices at TA > 85°CXXXXXXX
Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)Auto-Baud Detect1.10.1Auto-Baud Detect May Store Incorrect Count Value in the SPBRG RegistersXXXXX
ResetsRESET Instruction1.11.1Extended Reset if Clock is MFINTOSC or HFINTOSCXXXXXX
Master Synchronous Serial Port (MSSP)SPI Master Mode1.12.1The Buffer Full (BF) Bit or MSSP Interrupt Flag (SSPIF) Bit Becomes Set Half of a SCK Cycle EarlyXXXXXXX
Note: Only those issues indicated in the last column apply to the current silicon revision.