53.7.7 Status
| Name: | STATUS |
| Offset: | 0x07 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EOC1 | EOC0 | READY1 | READY0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – EOC1 DAC1 End of Conversion
This bit is cleared when DATA1 register is written.
| Value | Description |
|---|---|
| 0 | No conversion completed since last load of DATA1. |
| 1 | DAC1 conversion is complete, VOUT1 is stable. |
Bit 2 – EOC0 DAC0 End of Conversion
This bit is cleared when DATA0 register is written.
| Value | Description |
|---|---|
| 0 | No conversion completed since last load of DATA0. |
| 1 | DAC0 conversion is complete, VOUT0 is stable. |
Bit 1 – READY1 DAC1 Startup Ready
| Value | Description |
|---|---|
| 0 | DAC1 is not ready for conversion. |
| 1 | Startup time has elapsed, DAC1 is ready for conversion. |
Bit 0 – READY0 DAC0 Startup Ready
| Value | Description |
|---|---|
| 0 | DAC0 is not ready for conversion. |
| 1 | Startup time has elapsed, DAC0 is ready for conversion. |