53.7.12 Data DAC1

Note: This register is write-synchronized: SYNCBUSY.DATA1 must be checked to ensure the DATA1 register synchronization is complete.
Name: DATA1
Offset: 0x12
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized

Bit 15141312111098 
 DATA[15:8] 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 DATA[7:0] 
Access WWWWWWWW 
Reset 00000000 

Bits 15:0 – DATA[15:0] DAC1 Data

DATA1 register contains the 12-bit value that is converted to a voltage by the DAC1. The adjustment of these 12 bits within the 16-bit register is controlled by DACCTRL1.LEFTADJ:

- DATA[11:0] when DACCTRL1.LEFTADJ=0.

- DATA[15:4] when DACCTRL1.LEFTADJ=1.

In dithering mode (whatever DACCTRL1.LEFTADJ value):

- DATA[15:4] are the 12-bit converted by DAC1.

- DATA[3:0] are the dither bits.