53.7.2 Control B

Name: CTRLB
Offset: 0x01
Reset: 0x02
Property: PAC Write-Protection

Bit 76543210 
      REFSEL[1:0]DIFF 
Access R/WR/WR/W 
Reset 010 

Bits 2:1 – REFSEL[1:0] Reference Selection

This bit field selects the Reference Voltage for both DACs.

Note:
  1. The reference selection of the DAC will reset to ‘0’ (VREFAU) if the DAC Software Reset (CTRLA.SWRST) is used.
  2. When the internal bandgap reference (INTREF) is selected as reference voltage (CTRLB.REFSEL = 0x3), the DAC Startup Ready bits value (STATUS.READY0, STATUS.READY1) is not correct for the first DAC Conversion after device power-up or after wake-up from Standby Low-Power mode. Disregard STATUS.READY0 and STATUS.READY1 bits for the first DAC conversion and check instead that the Data Buffer 0/1 Empty bits are set (INTFLAG.EMPTY0 = 1, INTFLAG.EMPTY1 = 1).
ValueNameDescription
0x0 VREFAU Unbuffered external voltage reference (not buffered in DAC, direct connection)
0x1 AVDD Voltage supply
0x2 VREFAB Buffered external voltage reference (buffered in DAC). This buffered external voltage reference option can be used when the applied external input reference voltage has insufficient drive current.
0x3 INTREF Internal bandgap reference

Bit 0 – DIFF Differential Mode Enable

This bit defines the conversion mode for both DACs.

ValueDescription
0 Single mode
1 Differential mode