53.7 Register Summary
Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|
0x00 | CTRLA | 7:0 | ENABLE | SWRST | ||||||
0x01 | CTRLB | 7:0 | REFSEL[1:0] | DIFF | ||||||
0x02 | EVCTRL | 7:0 | INVEI1 | INVEI0 | EMPTYEO1 | EMPTYEO0 | STARTEI1 | STARTEI0 | ||
0x03 | Reserved | |||||||||
0x04 | INTENCLR | 7:0 | EMPTY1 | EMPTY0 | UNDERRUN1 | UNDERRUN0 | ||||
0x05 | INTENSET | 7:0 | EMPTY1 | EMPTY0 | UNDERRUN1 | UNDERRUN0 | ||||
0x06 | INTFLAG | 7:0 | EMPTY1 | EMPTY0 | UNDERRUN1 | UNDERRUN0 | ||||
0x07 | STATUS | 7:0 | EOC1 | EOC0 | READY1 | READY0 | ||||
0x08 | SYNCBUSY | 7:0 | DATABUF1 | DATABUF0 | DATA1 | DATA0 | ENABLE | SWRST | ||
15:8 | ||||||||||
23:16 | ||||||||||
31:24 | ||||||||||
0x0C | DACCTRL0 | 7:0 | DITHER | RUNSTDBY | CCTRL[1:0] | ENABLE | LEFTADJ | |||
15:8 | ||||||||||
0x0E | DACCTRL1 | 7:0 | DITHER | RUNSTDBY | CCTRL[1:0] | ENABLE | LEFTADJ | |||
15:8 | ||||||||||
0x10 | DATA0 | 7:0 | DATA[7:0] | |||||||
15:8 | DATA[15:8] | |||||||||
0x12 | DATA1 | 7:0 | DATA[7:0] | |||||||
15:8 | DATA[15:8] | |||||||||
0x14 | DATABUF0 | 7:0 | DATABUF[7:0] | |||||||
15:8 | DATABUF[15:8] | |||||||||
0x16 | DATABUF1 | 7:0 | DATABUF[7:0] | |||||||
15:8 | DATABUF[15:8] | |||||||||
0x18 | DBGCTRL | 7:0 | DBGRUN |