11.6 Crystal Oscillator

Table 11-8. 24 MHz Crystal Oscillator Characteristics
ParameterTest ConditionSymbolRatingUnit
MinTypMax
Crystal Oscillator frequencyFundamentalXtal24MHz
Internal parasitic capacitanceBetween XIN and XOUTCPARA24M0.60.70.8pF
Start-up timetON1ms
Drive levelPON400µW
Load capacitanceCLOAD418pF
Important: Locate the crystal as close as possible to the XOUT and XIN pins.
Figure 11-1. 24 MHz Crystal Oscillator Schematic
CX = 2 x (CXTAL – CPARA24M – CPCB /2)

Where CXTAL is the load capacitance of the crystal, CPARA24M is the internal parasitic impedance of the oscillator, typically 0.7pF and CPCB is the ground-referenced parasitic capacitance of the printed circuit board (PCB) on XIN and XOUT tracks.

Table 11-9 summarizes recommendations to be followed when choosing a crystal.

The drive level indicates power consumption by the crystal unit while the oscillation circuit works. Excessive drive level might cause unexpected change of frequency, crystal damage or shorter device lifetime. The drive level is given by the following formula:

Drive Level=ESR×I2

Where:
  • ESR is the equivalent series resistor (specified by the crystal manufacturer).
  • I is the current flowing through the crystal in RMS. If the waveform is sine wave or similar, the effective value is calculated by Ip-p/2√2.

To keep the drive level value inside the manufacturer range, it is required to limit the current that flows through the crystal. The total power dissipated by the crystal is proportional to RS (see Figure 11-1), so its value can be modified to obtain a drive level that complies with the requirements. As the value of RS also relates to the safety factor, there is a maximum value of RS that maintains a good safety factor and at the same time keeps the drive level below the crystal manufacturer maximum specifications.

Table 11-9. Recommended Crystal Characteristics
ParameterSymbolRatingUnit
MinTypMax
Equivalent Series ResistorESR100Ω
Motional capacitanceCM23.2fF
Shunt capacitanceCSHUNT1.3pF
Frequency tolerance10(1)25ppm
Notes:
  1. As a requirement of the G3-PLC specification, the System Clock tolerance shall be ±25 ppm maximum. In the case of PRIME specification, it shall be ±50 ppm maximum. In both cases, Microchip recommends choosing a crystal with a frequency tolerance below the specification requirement because it is dependent on production tolerance, temperature stability and age.