11.5 Power Consumption

The table below shows power consumption of the system (digital and analog) when it is used with typical AMR protocols. However, it is important to remember that different protocols, or even the same protocols used with different clock schemes or with different software implementations, can lead to other consumption figures.

Table 11-6. Full System Power Consumption
Frequency band Application Case Rating Unit
3V3 12V
Typ(1) Typ(1)

CENELEC-A

CENELEC-B

 Reception waiting for preamble detection 34 0.6 mA
Reception processing incoming frames 45 0.6
Transmission with internal driver 46 104
FCC Reception waiting for preamble detection 65 0.6
Reception processing incoming frames 87 0.6
Transmission with internal driver 91 166
Notes:
  1. TAMB = 25ºC, VDDIO = 3.3V, VDDIN = 3.3V and VDDIN_AN = 3.3V, G3-PLC

The table below shows power consumption of the analog IPs in the system. Analog parts are the PLL used for internal clock generation (supplied from VDDPLL pin) and the conversion module composed of the Programmable Gain Amplifier (PGA) and the Analog-to-Digital Converter (ADC), both supplied from VDDIN_AN pins.

Take maximum consumption cases into account for supply filter calculation. The supply voltage drop after the filters must be small enough to ensure the correct operation of the analog IPs. Voltage applied to VDDPLL and VDDIN_AN must always be greater than Vtypical-10%, VDDPLL > 1.08V and VDDIN_AN > 3.0V.

Table 11-7. Analog Power Consumption
Supply Block Application Case Rating Unit
Min Typ Max
VDDPLL PLL — — 1.7(1) 2.1(2) mA
VDDIN_AN PGA — — 1.5(3) 2.2(4)
ADC CENELEC-A / CENELEC-B — 7.5(3) 10.8(4)
FCC — 14.4(3) 20.9(4)
Notes:
  1. Typical case conditions: freq = 216 MHz, TAMB = 25ºC, VDDPLL = 1.2V
  2. Worst case conditions: freq = 216 MHz, TAMB = 125ºC, VDDPLL = 1.32V
  3. Typical case conditions: TJ = 25ºC, VDDIN_AN = 3.3V
  4. Worst case conditions: TJ = 125ºC, VDDIN_AN = 3.6V