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PolarFire FPGA Dynamic Reconfiguration Interface Application Note AN4592
PolarFire FPGA Dynamic Reconfiguration Interface Application Note AN4592
  1. Home
  2. 1 PolarFire FPGA Dynamic Reconfiguration Interface
  3. 1.3 Demo Design
  4. 1.3.1 Design Implementation
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AN4592

  • Introduction
  • 1 PolarFire FPGA Dynamic Reconfiguration Interface
    • 1.1 Design Requirements
    • 1.2 Prerequisites
    • 1.3 Demo Design
      • 1.3.1 Design Implementation
      • 1.3.2 IP Configuration
    • 1.4 Port Description
    • 1.5 Simulating the Design
    • 1.6 Simulation Flow
    • 1.7 Clocking Structure
    • 1.8 Reset Structure
  • 2 Run PROGRAM Action
  • 3 Running the Demo
  • 4 Appendix A: Programming the Device Using FlashPro Express
  • 5 Appendix B: Running the TCL Script
  • 6 Appendix C: PLL or DLL Placement with DRI
  • 7 Revision History
  • Microchip FPGA Support
  • Microchip Information

1.3.1 Design Implementation

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The following figure shows the top-level Libero design of the PolarFire Transceiver Dynamic Reconfiguration Interface design.

Figure 1-2. Top Level Libero Design
Important: For the latest SmartDesign, see the www.microchip.com/en-us/application-notes/AN4592.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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