36.7.9 Input Control

Note: This register is write-synchronized: SYNCBUSY.INPUTCTRL must be checked to ensure the INPUTCTRL register synchronization is complete.
Name: INPUTCTRL
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized

Bit 15141312111098 
    MUXNEG[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
    MUXPOS[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 12:8 – MUXNEG[4:0] Negative MUX Input Selection

These bits define the MUX selection for the negative ADC input.

ValueNameDescription
0x00 AIN0 ADC AIN0 pin
0x01 AIN1 ADC AIN1 pin
0x02 AIN2 ADC AIN2 pin
0x03 AIN3 ADC AIN3 pin
0x04 AIN4 ADC AIN4 pin
0x05 AIN5 ADC AIN5 pin
0x06 - 0x17 - Reserved
0x18 GND Internal ground
0x19 - 0x1F - Reserved

Bits 4:0 – MUXPOS[4:0] Positive MUX Input Selection

These bits define the MUX selection for the positive ADC input. If the internal INTREF voltage input channel is selected, then the Sampling Time Length bit group in the Sampling Control register must be written with a corresponding value.

ValueNameDescription
0x00 AIN0 ADC AIN0 pin
0x01 AIN1 ADC AIN1 pin
0x02 AIN2 ADC AIN2 pin
0x03 AIN3 ADC AIN3 pin
0x04 AIN4 ADC AIN4 pin
0x05 AIN5 ADC AIN5 pin
0x06 AIN6 ADC AIN6 pin
0x07 AIN7 ADC AIN7 pin
0x08 AIN8 ADC AIN8 pin
0x09 AIN9 ADC AIN9 pin
0x0A AIN10 ADC AIN10 pin
0x0B AIN11 ADC AIN11 pin
0xC - 0x18 - Reserved
0x19 INTREF Internal voltage reference, supplied by the bandgap (refer to SUPC.VREF.SEL for voltage level information)
0x1A SCALEDVDDCORE 1/4 Scaled VDDCORE Supply
0x1B SCALEDVDDANA 1/4 Scaled VDDANA Supply
0x1C - Reserved
0x1D - Reserved
0x1E - Reserved
0x1F - Reserved