36.7.6 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
      WINMONOVERRUNRESRDY 
Access R/WR/WR/W 
Reset 000 

Bit 2 – WINMON Window Monitor Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Window Monitor Interrupt bit, which enables the Window Monitor interrupt.

ValueDescription
0 The Window Monitor interrupt is disabled.
1 The Window Monitor interrupt is enabled.

Bit 1 – OVERRUN Overrun Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Overrun Interrupt bit, which enables the Overrun interrupt.

ValueDescription
0 The Overrun interrupt is disabled.
1 The Overrun interrupt is enabled.

Bit 0 – RESRDY Result Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Result Ready Interrupt bit, which enables the Result Ready interrupt.

ValueDescription
0 The Result Ready interrupt is disabled.
1 The Result Ready interrupt is enabled.