36.7.12 Sampling Time Control

Note: This register is write-synchronized: SYNCBUSY.SAMPCTRL must be checked to ensure the SAMPCTRL register synchronization is complete.

Name:	SAMPCTRL
Offset:	0x0D
Reset:	0x00
Property:	PAC Write-Protection, Write-Synchronized


Bit	7	6	5	4	3	2	1	0
	OFFCOMP		SAMPLEN[5:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		0	0	0	0	0	0

Bit 7 – OFFCOMP Comparator Offset Compensation Enable

Setting this bit enables the offset compensation for each sampling period to ensure low offset and immunity to temperature or voltage drift. This compensation increases the sampling time by three clock cycles that results in a fixed sampling duration of 4 CLK_ADC cycles.

This bit must be set to zero to validate the SAMPLEN value. It’s not possible to use OFFCOMP=1 and SAMPLEN>0.

Bits 5:0 – SAMPLEN[5:0] Sampling Time Length

These bits control the ADC sampling time (T_SAMP) in number of ADC Clock Period (CLK_ADC aka TAD), depending of the prescaler value, thus controlling the ADC input impedance. Sampling time is set according to the equation:

{(T}_{S A M P}) = (SAMPLEN + 1) \cdot (T A D)

SAMPLEN is only available when OFFCOMP=0.

Note: Refer to 44.14 ADC Electrical Specifications for T_SAMP computation.