36.7.10 Control C
Note: This register is write-synchronized: SYNCBUSY.CTRLC must be checked to ensure the
CTRLC register synchronization is complete.
| Name: | CTRLC |
| Offset: | 0x0A |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DUALSEL[1:0] | WINMODE[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| R2R | RESSEL[1:0] | CORREN | FREERUN | LEFTADJ | DIFFMODE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 13:12 – DUALSEL[1:0] Dual Mode Trigger Selection
These bits define the trigger mode. These bits are available in the host ADC and have no effect if the host-client operation is disabled (ADC1.CTRLA.SLAVEEN=0).
| Value | Name | Description |
|---|---|---|
| 0x0 | BOTH | Start event or software trigger will start a conversion on both ADCs. |
| 0x1 | INTERLEAVE | Start event or software trigger will alternatively start a conversion on ADC0 and ADC1. |
| 0x2 - 0x3 | - | Reserved |
Bits 10:8 – WINMODE[2:0] Window Monitor Mode
These bits enable and define the window monitor mode.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | No window mode (default) |
| 0x1 | MODE1 | RESULT > WINLT |
| 0x2 | MODE2 | RESULT < WINUT |
| 0x3 | MODE3 | WINLT < RESULT < WINUT |
| 0x4 | MODE4 | WINUT < RESULT < WINLT |
| 0x5 - 0x7 | Reserved |
Bit 7 – R2R Rail-to-Rail Operation
| Value | Description |
|---|---|
| 0 | Disable rail-to-rail operation. |
| 1 | Enable rail-to-rail operation to increase the allowable range of the input common mode voltage (VCMIN). When R2R is one, a sampling period of four cycles is required. Offset compensation (SAMPCTRL.OFFCOMP) must be written to one when using this period. |
Bits 5:4 – RESSEL[1:0] Conversion Result Resolution
These bits define whether the ADC completes the conversion 12-, 10- or 8-bit result resolution.
| Value | Name | Description |
|---|---|---|
| 0x0 | 12BIT | 12-bit result |
| 0x1 | 16BIT | Accumulation or Oversampling and Decimation modes |
| 0x2 | 10BIT | 10-bit result |
| 0x3 | 8BIT | 8-bit result |
Bit 3 – CORREN Digital Correction Logic Enabled
| Value | Description |
|---|---|
| 0 | Disable the digital result correction. |
| 1 | Enable the digital result correction. The ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCORR and OFFSETCORR registers. Conversion time will be increased by 13 cycles according to the value in the Offset Correction Value bit group in the Offset Correction register. |
Bit 2 – FREERUN Free Running Mode
| Value | Description |
|---|---|
| 0 | The ADC run in single conversion mode. |
| 1 | The ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. |
Bit 1 – LEFTADJ Left-Adjusted Result
| Value | Description |
|---|---|
| 0 | The ADC conversion result is right-adjusted in the RESULT register. |
| 1 | The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. |
Bit 0 – DIFFMODE Differential Mode
| Value | Description |
|---|---|
| 0 | The ADC is running in singled-ended mode. |
| 1 | The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. |