33.8 Two-Wire Serial Interface Characteristics

Table in this section describes the requirements for devices connected to the two-wire Serial Bus. The two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 33-5.

Table 33-9. Two-Wire Serial Bus Requirements
Symbol	Parameter	Condition	Min.	Max	Units
V_IL	Input Low-voltage		-0.5	0.3 V_CC	V
V_IH	Input High-voltage		0.7 V_CC	V_CC + 0.5	V
V_hys⁽¹⁾	Hysteresis of Schmitt Trigger Inputs		0.05 V_CC⁽²⁾	–	V
V_OL⁽¹⁾	Output Low-voltage	3mA sink current	0	0.4	V
t_r⁽¹⁾	Rise Time for both SDA and SCL		20 + 0.1C_b⁽³⁾⁽²⁾	300	ns
t_of⁽¹⁾	Output Fall Time from V_IHmin to V_ILmax	10 pF < C_b < 400 pF⁽³⁾	20 + 0.1C_b⁽³⁾⁽²⁾	250	ns
t_SP⁽¹⁾	Spikes Suppressed by Input Filter		0	50⁽²⁾	ns
I_i	Input Current each I/O Pin	0.1V_CC < V_i < 0.9V_CC	-10	10	μA
C_i⁽¹⁾	Capacitance for each I/O Pin		–	10	pF
f_SCL	SCL Clock Frequency	f_CK⁽⁴⁾ > max(16f_SCL, 250 kHz)⁽⁵⁾	0	400	kHz
Rp	Value of Pull-up resistor	f_SCL ≤ 100 kHz	$\frac{V_{CC} - 0.4V}{3mA}$	$\frac{1000ns}{C_{b}}$	$Ω$
Rp	Value of Pull-up resistor	f_SCL > 100 kHz	$\frac{V_{CC} - 0.4V}{3mA}$	$\frac{300ns}{C_{b}}$	$Ω$
t_HD;STA	Hold Time (repeated) START Condition	f_SCL ≤ 100 kHz	4.0	–	μs
t_HD;STA	Hold Time (repeated) START Condition	f_SCL > 100 kHz	0.6	–	μs
t_LOW	Low Period of the SCL Clock	f_SCL ≤ 100 kHz	4.7	–	μs
t_LOW	Low Period of the SCL Clock	f_SCL > 100 kHz	1.3	–	μs
t_HIGH	High period of the SCL clock	f_SCL ≤ 100 kHz	4.0	–	μs
t_HIGH	High period of the SCL clock	f_SCL > 100 kHz	0.6	–	μs
t_SU;STA	Set-up time for a repeated START condition	f_SCL ≤ 100 kHz	4.7	–	μs
t_SU;STA	Set-up time for a repeated START condition	f_SCL > 100 kHz	0.6	–	μs
t_HD;DAT	Data hold time	f_SCL ≤ 100 kHz	0	3.45	μs
t_HD;DAT	Data hold time	f_SCL > 100 kHz	0	0.9	μs
t_SU;DAT	Data setup time	f_SCL ≤ 100 kHz	250	–	ns
t_SU;DAT	Data setup time	f_SCL > 100 kHz	100	–	ns
t_SU;STO	Setup time for STOP condition	f_SCL ≤ 100 kHz	4.0	–	μs
t_SU;STO	Setup time for STOP condition	f_SCL > 100 kHz	0.6	–	μs
t_BUF	Bus free time between a STOP and START condition	f_SCL ≤ 100 kHz	4.7	–	μs
t_BUF	Bus free time between a STOP and START condition	f_SCL > 100 kHz	1.3	–	μs

Note:

This parameter is characterized and not 100% tested.
Required only for f_SCL > 100 kHz.
C_b = capacitance of one bus line in pF.
f_CK = CPU clock frequency.
This requirement applies to all two-wire Serial Interface operation. Other devices connected to the two-wire Serial Bus need only obey the general f_SCL requirement.

ATmega328PB

33.8 Two-Wire Serial Interface Characteristics