33.7 SPI Timing Characteristics

Table 33-8. SPI Timing Parameters
DescriptionModeMin.TypMaxUnits
1SCK periodMaster-See Table 23-5-ns
2SCK high/lowMaster-50% duty cycle-
3Rise/Fall timeMaster-3.6-
4SetupMaster-10-
5HoldMaster-10-
6Out to SCKMaster-0.5 • tsck-
7SCK to outMaster-10-
8SCK to out highMaster-10-
9SS low to outSlave-15-
10SCK periodSlave4 • tck--
11SCK high/low(1)Slave2 • tck--
12Rise/Fall timeSlave--1600
13SetupSlave10--
14HoldSlavetck--
15SCK to outSlave-15-
16SCK to SS highSlave20--
17SS high to tri-stateSlave-10-
18SS low to SCKSlave2 • tck--
Note:
  1. In SPI Programming mode the minimum SCK high/low period is:

  • 2 tCLCL for fCK < 12 MHz

  • 3 tCLCL for fCK > 12 MHz
Figure 33-3. SPI Interface Timing Requirements (Master Mode)
Figure 33-4. SPI Interface Timing Requirements (Slave Mode)