36.6.1 ISI Configuration 1 Register
| Name: | ISI_CFG1 |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SFD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SLD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| THMASK[1:0] | FULL | DISCR | FRATE[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRC_SYNC | EMB_SYNC | GRAYLE | PIXCLK_POL | VSYNC_POL | HSYNC_POL | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:24 – SFD[7:0] Start of Frame Delay
SFD lines are skipped at the beginning of the frame.
Bits 23:16 – SLD[7:0] Start of Line Delay
SLD pixel clock periods to wait before the beginning of a line.
Bits 14:13 – THMASK[1:0] Threshold Mask
| Value | Name | Description |
|---|---|---|
| 0 | BEATS_4 | Only 4 beats AHB burst allowed |
| 1 | BEATS_8 | Only 4 and 8 beats AHB burst allowed |
| 2 | BEATS_16 | 4, 8 and 16 beats AHB burst allowed |
Bit 12 – FULL Full Mode is Allowed
| Value | Description |
|---|---|
| 0 | The codec frame is transferred to memory when an available frame slot is detected. |
| 1 | Both preview and codec DMA channels are operating simultaneously. |
Bit 11 – DISCR Disable Codec Request
| Value | Description |
|---|---|
| 0 | Codec datapath DMA interface requires a request to restart. |
| 1 | Codec datapath DMA automatically restarts. |
Bits 10:8 – FRATE[2:0] Frame Rate [0..7]
| Value | Description |
|---|---|
| 0 | All the frames are captured, else one frame every FRATE + 1 is captured. |
Bit 7 – CRC_SYNC Embedded Synchronization Correction
| Value | Description |
|---|---|
| 0 | No CRC correction is performed on embedded synchronization. |
| 1 | CRC correction is performed. If the correction is not possible, the current frame is discarded and the CRC_ERR bit is set in the ISI_SR. |
Bit 6 – EMB_SYNC Embedded Synchronization
| Value | Description |
|---|---|
| 0 | Synchronization by HSYNC, VSYNC. |
| 1 | Synchronization by embedded synchronization sequence SAV/EAV. |
Bit 5 – GRAYLE Grayscale Little Endian
Refer to Table 36-8 and Table 36-9 for details.
| Value | Description |
|---|---|
| 0 |
The two pixels are represented in big-endian format within a 32-bit register. |
| 1 |
The two pixels are represented in little-endian format within a 32-bit register. |
Bit 4 – PIXCLK_POL Pixel Clock Polarity
| Value | Description |
|---|---|
| 0 | Data is sampled on rising edge of pixel clock. |
| 1 | Data is sampled on falling edge of pixel clock. |
Bit 3 – VSYNC_POL Vertical Synchronization Polarity
| Value | Description |
|---|---|
| 0 | VSYNC active high. |
| 1 | VSYNC active low. |
Bit 2 – HSYNC_POL Horizontal Synchronization Polarity
| Value | Description |
|---|---|
| 0 | HSYNC active high. |
| 1 | HSYNC active low. |