36.6.19 DMA Preview Control Register
Name: | ISI_DMA_P_CTRL |
Offset: | 0x48 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
P_DONE | P_IEN | P_WB | P_FETCH | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit 3 – P_DONE Preview Transfer Done
This bit is only updated in the memory.
Value | Description |
---|---|
0 | The transfer related to this descriptor has not been performed. |
1 | The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer, when writeback operation is enabled. |
Bit 2 – P_IEN Transfer Done Flag Control
Value | Description |
---|---|
0 | Preview transfer done flag generation is enabled. |
1 | Preview transfer done flag generation is disabled. |
Bit 1 – P_WB Descriptor Writeback Control Bit
Value | Description |
---|---|
0 | Preview channel writeback operation is disabled. |
1 | Preview channel writeback operation is enabled. |
Bit 0 – P_FETCH Descriptor Fetch Control Bit
Value | Description |
---|---|
0 | Preview channel fetch operation is disabled. |
1 | Preview channel fetch operation is enabled. |