36.6 Register Summary

Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller.
OffsetNameBit Pos.76543210
0x00ISI_CFG17:0CRC_SYNCEMB_SYNCGRAYLEPIXCLK_POLVSYNC_POLHSYNC_POL  
15:8 THMASK[1:0]FULLDISCRFRATE[2:0]
23:16SLD[7:0]
31:24SFD[7:0]
0x04ISI_CFG27:0IM_VSIZE[7:0]
15:8COL_SPACERGB_SWAPGRAYSCALERGB_MODEGS_MODEIM_VSIZE[10:8]
23:16IM_HSIZE[7:0]
31:24RGB_CFG[1:0]YCC_SWAP[1:0] IM_HSIZE[10:8]
0x08ISI_PSIZE7:0PREV_VSIZE[7:0]
15:8      PREV_VSIZE[9:8]
23:16PREV_HSIZE[7:0]
31:24      PREV_HSIZE[9:8]
0x0CISI_PDECF7:0DEC_FACTOR[7:0]
15:8        
23:16        
31:24        
0x10ISI_Y2R_SET07:0C0[7:0]
15:8C1[7:0]
23:16C2[7:0]
31:24C3[7:0]
0x14ISI_Y2R_SET17:0C4[7:0]
15:8 CboffCroffYoff   C4[8]
23:16        
31:24        
0x18ISI_R2Y_SET07:0 C0[6:0]
15:8 C1[6:0]
23:16 C2[6:0]
31:24       Roff
0x1CISI_R2Y_SET17:0 C3[6:0]
15:8 C4[6:0]
23:16 C5[6:0]
31:24       Goff
0x20ISI_R2Y_SET27:0 C6[6:0]
15:8 C7[6:0]
23:16 C8[6:0]
31:24       Boff
0x24ISI_CR7:0     ISI_SRSTISI_DISISI_EN
15:8       ISI_CDC
23:16        
31:24        
0x28ISI_SR7:0     SRSTDIS_DONEENABLE
15:8     VSYNC CDC_PND
23:16    SIP CXFR_DONEPXFR_DONE
31:24    FR_OVRCRC_ERRC_OVRP_OVR
0x2CISI_IER7:0     SRSTDIS_DONE 
15:8     VSYNC  
23:16      CXFR_DONEPXFR_DONE
31:24    FR_OVRCRC_ERRC_OVRP_OVR
0x30ISI_IDR7:0     SRSTDIS_DONE 
15:8     VSYNC  
23:16      CXFR_DONEPXFR_DONE
31:24    FR_OVRCRC_ERRC_OVRP_OVR
0x34ISI_IMR7:0     SRSTDIS_DONE 
15:8     VSYNC  
23:16      CXFR_DONEPXFR_DONE
31:24    FR_OVRCRC_ERRC_OVRP_OVR
0x38ISI_DMA_CHER7:0      C_CH_ENP_CH_EN
15:8        
23:16        
31:24        
0x3CISI_DMA_CHDR7:0      C_CH_DISP_CH_DIS
15:8        
23:16        
31:24        
0x40ISI_DMA_CHSR7:0      C_CH_SP_CH_S
15:8        
23:16        
31:24        
0x44ISI_DMA_P_ADDR7:0P_ADDR[5:0]  
15:8P_ADDR[13:6]
23:16P_ADDR[21:14]
31:24P_ADDR[29:22]
0x48ISI_DMA_P_CTRL7:0    P_DONEP_IENP_WBP_FETCH
15:8        
23:16        
31:24        
0x4CISI_DMA_P_DSCR7:0P_DSCR[5:0]  
15:8P_DSCR[13:6]
23:16P_DSCR[21:14]
31:24P_DSCR[29:22]
0x50ISI_DMA_C_ADDR7:0C_ADDR[5:0]  
15:8C_ADDR[13:6]
23:16C_ADDR[21:14]
31:24C_ADDR[29:22]
0x54ISI_DMA_C_CTRL7:0    C_DONEC_IENC_WBC_FETCH
15:8        
23:16        
31:24        
0x58ISI_DMA_C_DSCR7:0C_DSCR[5:0]  
15:8C_DSCR[13:6]
23:16C_DSCR[21:14]
31:24C_DSCR[29:22]

0x5C

...

0xE3

Reserved         
0xE4ISI_WPMR7:0       WPEN
15:8WPKEY[7:0]
23:16WPKEY[15:8]
31:24WPKEY[23:16]
0xE8ISI_WPSR7:0       WPVS
15:8WPVSRC[7:0]
23:16WPVSRC[15:8]
31:24