51.7.25 AFEC Correction Select Register
This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
| Name: | AFEC_COSR |
| Offset: | 0xD0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSEL | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – CSEL Sample & Hold unit Correction Select
Selects the Sample & Hold unit to be displayed in the AFEC_CVR.
0 = Select lower channels
1 = Select upper channels