51.7.2 AFEC Mode Register
This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
| Name: | AFEC_MR |
| Offset: | 0x04 |
| Reset: | 0x30000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| USEQ | TRANSFER[1:0] | TRACKTIM[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ONE | STARTUP[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PRESCAL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FREERUN | FWUP | SLEEP | TRGSEL[2:0] | TRGEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 31 – USEQ User Sequence Enable
| Value | Name | Description |
|---|---|---|
| 0 | NUM_ORDER | Normal mode: the controller converts channels in a simple numeric order. |
| 1 | REG_ORDER | User Sequence mode: the sequence is as defined in AFEC_SEQ1R and AFEC_SEQ1R. |
Bits 29:28 – TRANSFER[1:0] Transfer Period
Set the period (in number of ADC clock) between a start command and the selection of the analog channel.
| Value | Description |
|---|---|
| 0x0 | Forbidden |
| 0x1 | Forbidden |
| 0x2 | Recommended to optimize the conversion ( 8 AFE clocks) |
| 0x3 | Default value (9 AFE clocks) |
Bits 27:24 – TRACKTIM[3:0] Tracking Time
Inherent tracking time is always 15 AFE clock cycles. Do not modify this field.
Bit 23 – ONE One
This bit must be written to 1.
Bits 19:16 – STARTUP[3:0] Startup Time
| Value | Name | Description |
|---|---|---|
| 0 | SUT0 | 0 periods of AFE clock |
| 1 | SUT8 | 8 periods of AFE clock |
| 2 | SUT16 | 16 periods of AFE clock |
| 3 | SUT24 | 24 periods of AFE clock |
| 4 | SUT64 | 64 periods of AFE clock |
| 5 | SUT80 | 80 periods of AFE clock |
| 6 | SUT96 | 96 periods of AFE clock |
| 7 | SUT112 | 112 periods of AFE clock |
| 8 | SUT512 | 512 periods of AFE clock |
| 9 | SUT576 | 576 periods of AFE clock |
| 10 | SUT640 | 640 periods of AFE clock |
| 11 | SUT704 | 704 periods of AFE clock |
| 12 | SUT768 | 768 periods of AFE clock |
| 13 | SUT832 | 832 periods of AFE clock |
| 14 | SUT896 | 896 periods of AFE clock |
| 15 | SUT960 | 960 periods of AFE clock |
Bits 15:8 – PRESCAL[7:0] Prescaler Rate Selection
PRESCAL = fperipheral clock/ fAFE Clock - 1
When PRESCAL is cleared, no conversion is performed.
Bit 7 – FREERUN Free Run Mode
| Value | Name | Description |
|---|---|---|
| 0 | OFF | Normal mode |
| 1 | ON | Free Run mode: never wait for any trigger. |
Bit 6 – FWUP Fast Wakeup
| Value | Name | Description |
|---|---|---|
| 0 | OFF | Normal Sleep mode: the sleep mode is defined by the SLEEP bit. |
| 1 | ON | Fast Wakeup Sleep mode: the voltage reference is ON between conversions and AFE is OFF. |
Bit 5 – SLEEP Sleep Mode
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Normal mode: the AFE and reference voltage circuitry are kept ON between conversions. |
| 1 | SLEEP | Sleep mode: the AFE and reference voltage circuitry are OFF between conversions. |
Bits 3:1 – TRGSEL[2:0] Trigger Selection
| Value | Name | Description |
|---|---|---|
| 0 | AFEC_TRIG0 | AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 |
| 1 | AFEC_TRIG1 | TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 |
| 2 | AFEC_TRIG2 | TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 |
| 3 | AFEC_TRIG3 | TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 |
| 4 | AFEC_TRIG4 | PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 |
| 5 | AFEC_TRIG5 | PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 |
| 6 | AFEC_TRIG6 | Analog Comparator |
| 7 | Reserved |
Bit 0 – TRGEN Trigger Enable
| Value | Name | Description |
|---|---|---|
| 0 | DIS | Hardware triggers are disabled. Starting a conversion is only possible by software. |
| 1 | EN | The hardware trigger selected by the TRGSEL field is enabled. |