51.7.3 AFEC Extended Mode Register
This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
| Name: | AFEC_EMR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SIGNMODE[1:0] | STM | TAG | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RES[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMPFILTER[1:0] | CMPALL | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMPSEL[4:0] | CMPMODE[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 29:28 – SIGNMODE[1:0] Sign Mode
| Value | Name | Description |
|---|---|---|
| 0 | SE_UNSG_DF_SIGN | Single-Ended channels: unsigned conversions. Differential channels: signed conversions. |
| 1 | SE_SIGN_DF_UNSG | Single-Ended channels: signed conversions. Differential channels: unsigned conversions. |
| 2 | ALL_UNSIGNED | All channels: unsigned conversions. |
| 3 | ALL_SIGNED | All channels: signed conversions. |
Bit 25 – STM Single Trigger Mode
| Value | Description |
|---|---|
| 0 | Multiple triggers are required to get an averaged result. |
| 1 | Only a single trigger is required to get an averaged value. |
Bit 24 – TAG Tag for AFEC_LCDR
| Value | Description |
|---|---|
| 0 | Clears CHNB in AFEC_LCDR. |
| 1 | Appends the channel number to the conversion result in AFEC_LCDR. |
Bits 18:16 – RES[2:0] Resolution
| Value | Name | Description |
|---|---|---|
| 0 | NO_AVERAGE | 12-bit resolution, AFE sample rate is maximum (no averaging). |
| 1 | LOW_RES | 10-bit resolution, AFE sample rate is maximum (no averaging). |
| 2 | OSR4 | 13-bit resolution, AFE sample rate divided by 4 (averaging). |
| 3 | OSR16 | 14-bit resolution, AFE sample rate divided by 16 (averaging). |
| 4 | OSR64 | 15-bit resolution, AFE sample rate divided by 64 (averaging). |
| 5 | OSR256 | 16-bit resolution, AFE sample rate divided by 256 (averaging). |
Bits 13:12 – CMPFILTER[1:0] Compare Event Filtering
Number of consecutive compare events necessary to raise the flag = CMPFILTER+1.
When programmed to ‘0’, the flag rises as soon as an event occurs.
Bit 9 – CMPALL Compare All Channels
| Value | Description |
|---|---|
| 0 | Only the channel indicated in CMPSEL field is compared. |
| 1 | All channels are compared. |
Bits 7:3 – CMPSEL[4:0] Comparison Selected Channel
If CMPALL = 0: CMPSEL indicates which channel has to be compared.
If CMPALL = 1: No effect.
Bits 1:0 – CMPMODE[1:0] Comparison Mode
| Value | Name | Description |
|---|---|---|
| 0 | LOW | Generates an event when the converted data is lower than the low threshold of the window. |
| 1 | HIGH | Generates an event when the converted data is higher than the high threshold of the window. |
| 2 | IN | Generates an event when the converted data is in the comparison window. |
| 3 | OUT | Generates an event when the converted data is out of the comparison window. |