51.7.23 AFEC Analog Control Register
This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
Name: | AFEC_ACR |
Offset: | 0x94 |
Reset: | 0x00000100 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
IBCTL[1:0] | |||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 1 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PGA1EN | PGA0EN | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bits 9:8 – IBCTL[1:0] AFE Bias Current Control
Adapts performance versus power consumption. (Refer to AFE Characteristics in section “Electrical Characteristics”.)
Bit 3 – PGA1EN PGA1 Enable
Value | Description |
---|---|
0 | Programmable Gain Amplifier is disabled. |
1 | Programmable Gain Amplifier is enabled. |
Bit 2 – PGA0EN PGA0 Enable
Value | Description |
---|---|
0 | Programmable Gain Amplifier is disabled. |
1 | Programmable Gain Amplifier is enabled. |