51.7.13 AFEC Interrupt Status Register
| Name: | AFEC_ISR |
| Offset: | 0x30 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TEMPCHG | COMPE | GOVRE | DRDY | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EOC11 | EOC10 | EOC9 | EOC8 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 30 – TEMPCHG Temperature Change (cleared on read)
| Value | Description |
|---|---|
| 0 |
No comparison match (defined in AFEC_TEMPCMPR) occurred since the last read of AFEC_ISR. |
| 1 |
The temperature value reported on AFEC_CDR (AFEC_CSELR.CSEL = 11) has changed since the last read of AFEC_ISR, according to what is defined in the Temperature Mode register (AFEC_TEMPMR) and the Temperature Compare Window register (AFEC_TEMPCWR). |
Bit 26 – COMPE Comparison Error (cleared by reading AFEC_ISR)
| Value | Description |
|---|---|
| 0 |
No comparison error since the last read of AFEC_ISR. |
| 1 |
At least one comparison error has occurred since the last read of AFEC_ISR. |
Bit 25 – GOVRE General Overrun Error (cleared by reading AFEC_ISR)
| Value | Description |
|---|---|
| 0 |
No general overrun error occurred since the last read of AFEC_ISR. |
| 1 |
At least one general overrun error has occurred since the last read of AFEC_ISR. |
Bit 24 – DRDY Data Ready (cleared by reading AFEC_LCDR)
| Value | Description |
|---|---|
| 0 |
No data has been converted since the last read of AFEC_LCDR. |
| 1 |
At least one data has been converted and is available in AFEC_LCDR. |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – EOCx End of Conversion x (cleared by reading AFEC_CDRx)
| Value | Description |
|---|---|
| 0 |
The corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the AFEC_CDR if the CSEL bit is programmed with ‘x’ in the AFEC_CSELR. |
| 1 |
The corresponding analog channel is enabled and conversion is complete. |