58.13.1.10.1 USART SPI Timings
Timings are given in the following domains:
- 3.3V domain: VDDIO from 2.85V to 3.6V,
maximum external capacitor = 40 pF
Table 58-60. USART SPI Timings Symbol Parameter Conditions Min Max Unit Host Mode SPI0 SCK Period 1.7V domain
3.3V domain
MCK/6
MCK/6
–
–
ns SPI1 Input Data Setup Time 1.7V domain
3.3V domain
2.8
2.5
–
–
ns SPI2 Input Data Hold Time 1.7V domain
3.3V domain
0.5
0.2
–
–
ns SPI3 Chip Select Active to Serial Clock 1.7V domain
3.3V domain
-1.1
-0.9
–
–
ns SPI4 Output Data Setup Time 1.7V domain
3.3V domain
-1.9
-1.9
10.9
10.4
ns SPI5 Serial Clock to Chip Select Inactive 1.7V domain
3.3V domain
-2.4
-2.4
-1.9
-1.9
ns Client Mode SPI6 SCK falling to MISO 1.7V domain
3.3V domain
3.6
2.9
16.8
13.9
ns SPI7 MOSI Setup time before SCK rises 1.7V domain
3.3V domain
2.4
2.0
–
–
ns SPI8 MOSI Hold time after SCK rises 1.7V domain
3.3V domain
0.4
0.2
–
–
ns SPI9 SCK rising to MISO 1.7V domain
3.3V domain
3.5
3.0
16.2
13.5
ns SPI10 MOSI Setup time before SCK falls 1.7V domain
3.3V domain
2.2
2.1
–
–
ns SPI11 MOSI Hold time after SCK falls 1.7V domain
3.3V domain
0.6
0.4
–
–
ns SPI12 NPCS0 setup to SCK rising 1.7V domain
3.3V domain
1.6
0.6
–
–
ns SPI13 NPCS0 hold after SCK falling 1.7V domain
3.3V domain
1.1
0.6
–
–
ns SPI14 NPCS0 setup to SCK falling 1.7V domain
3.3V domain
1.3
0.6
–
–
ns SPI15 NPCS0 hold after SCK rising 1.7V domain
3.3V domain
0.9
0.7
–
–
ns