58.13.1.6.2 SPI Timings

Timings are given in the following domains:

  • 1.8V domain: VDDIO from 1.7V to 1.95V, maximum external capacitor = 20 pF
  • 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF

    Table 58-55. SPI Timings
    SymbolParameterConditionsMinMaxUnit
    SPI0MISO Setup time before SPCK rises (Host)3.3V domain12.4ns
    1.8V domain14.6ns
    SPI1MISO Hold time after SPCK rises (Host)3.3V domain0ns
    1.8V domain0ns
    SPI2SPCK rising to MOSI Delay (Host)3.3V domain-3.72.2ns
    1.8V domain-3.82.7ns
    SPI3MISO Setup time before SPCK falls (Host)3.3V domain12.6ns
    1.8V domain15.13ns
    SPI4MISO Hold time after SPCK falls (Host)3.3V domain0ns
    1.8V domain0ns
    SPI5SPCK falling to MOSI Delay (Host)3.3V domain-3.62.0ns
    1.8V domain-3.32.8ns
    SPI6SPCK falling to MISO Delay (Client)3.3V domain3.011.9ns
    1.8V domain3.513.9ns
    SPI7MOSI Setup time before SPCK rises (Client)3.3V domain1.2ns
    1.8V domain1.5ns
    SPI8MOSI Hold time after SPCK rises (Client)3.3V domain0.6ns
    1.8V domain0.8ns
    SPI9SPCK rising to MISO Delay (Client)3.3V domain3.012.0ns
    1.8V domain3.413.7ns
    SPI10MOSI Setup time before SPCK falls (Client)3.3V domain1.2ns
    1.8V domain1.5ns
    SPI11MOSI Hold time after SPCK falls (Client)3.3V domain0.6ns
    1.8V domain0.8ns
    SPI12NPCS setup to SPCK rising (Client)3.3V domain3.9ns
    1.8V domain4.4ns
    SPI13NPCS hold after SPCK falling (Client)3.3V domain0ns
    1.8V domain0ns
    SPI14NPCS setup to SPCK falling (Client)3.3V domain4.0ns
    1.8V domain4.1ns
    SPI15NPCS hold after SPCK falling (Client)3.3V domain0ns
    1.8V domain0ns

Note that in SPI Host mode, the device does not sample the data (MISO) on the opposite edge where the data clocks out (MOSI), but the same edge is used. See Figure 57-19 and Figure 57-20.