1.2 Pin Details

The following figure illustrates the pin diagram of the IS2062GM.

Figure 1-2. IS2062GM PIN DIAGRAM

The following figure illustrates the pin diagram of the IS2064GM.

Figure 1-3. IS2064GM PIN DIAGRAM
  1. IS2064GM-0L3 does not support an analog output from the DAC. The * on AOHPR, AOHPM, and AOHPL reflect the affected pins.

The following figure illustrates the pin diagram of the IS2064S.

Figure 1-4. IS2064S PIN DIAGRAM

The following figure illustrates the pin diagram of the IS2064B.

Figure 1-5. IS2064B PIN DIAGRAM

The following table provides the pin description of the IS2062GM, IS2064GM, IS2064S and IS2064B.

Note: The conventions used in the below table are indicated as follows:
  • I = Input pin
  • O = Output pin
  • I/O = Input/Output pin
  • P = Power pin
Table 1-2. PIN DESCRIPTION
IS2062GM Pin NoIS2064GM-012 and IS2064S Pin NoIS2064GM-0L3 Pin NoIS2064B Ball NoPin TypePin NameDescription
5311—PVDDAOPower supply (3.0V to 3.6V) dedicated to codec output amplifiers; connect to CODEC_VO pin
542—A4OAOHPMHeadphone common mode output/sense input
553—A3OAOHPLLeft channel, analog headphone output
5644A2PVDDAAnalog reference voltage. Do not connect, for internal use only
155B3PVCOMInternal biasing voltage for codec, connect a 4.7 μF capacitor to ground
466C1IMIC_N1MIC1 mono differential analog negative input
577D1IMIC_P1MIC1 mono differential analog positive input
2——A1IMIC_N2MIC2 mono differential analog negative input
3——B1IMIC_P2MIC2 mono differential analog positive input
688C2PMIC_BIASElectric microphone biasing voltage
799E1IAIRRight channel, single-ended analog input
81010F1IAILLeft channel, single-ended analog input
91111D2PVDD_CORECore 1.2V power input; connect to CLDO_O pin; connect to GND through a 1 μF (X5R/X7R) capacitor
101212—OP1_2I2C SCL (Internal EEPROM clock), do not connect
111313E2I/OP1_3I2C SDA (Internal EEPROM data) requires external 4.7 kOhm pull-up resistor
121414F2IRST_NSystem Reset (active-low)
131515B2PVDD_IOI/O power supply input (3.0V to 3.6V); connect to LDO31_VO; connect to GND through a 1 μF (X5R/X7R) capacitor
141616G1I/OP0_1Configurable control or indication pin (Internally pulled up, if configured as an input)
  • FWD key when Class 2 RF (default), active-low
  • Class 1 Tx control signal for external RF Tx/Rx switch, active-high
151717G2I/OP2_4

For IS2062GM/64GM (Flash variant):

External address bus negative, System configuration pin along with the P2_0 and EAN pins can be used to set the SoC in any one of the following three modes:
  • Application mode (for normal operation)
  • Test mode (to change EEPROM values), and
  • Write Flash mode (to load a new firmware into the SoC), see Table 6-1

For IS2064S/B (ROM variant): Do not connect this pin

161818H2I/OP0_4Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • Out_Ind_1
171919H3IP1_5Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • Slide switch detector, active-high
  • Out_Ind_1
  • Master/Slave mode control
182020H4IHCI_RXDHCI UART data input
192121H5OHCI_TXDHCI UART data output
202222H1PCODEC_VOLDO output for codec power
212323J1PLDO31_VINLDO input, connect to SYS_PWR
222424J2ILDO31_VO3V LDO output for VDD_IO power, do not calibrate
232525J3PADAP_IN5V power adapter input, used to charge the battery in case of Li-Ion battery power applications
242626J4PBAT_IN

Power Supply input.

Voltage range: 3.2V to 4.2V. Source can either be a Li-Ion battery or any other power rail on the host board

252727H6PAMB_DETAnalog input for ambient temperature detection
262828J5PSAR_VDDSAR 1.8V input; connect to BK_O pin
272929J6PSYS_PWRSystem power output derived from the ADAP_IN or BAT_IN. Do not connect, for internal use only
283030J7IBK_VDD1.8V buck VDD power input; connect to SYS_PWR pin
293131J8IBK_LX1.8V buck regulator feedback path
303232J9IBK_O1.8V buck regulator output. Do not connect to other devices. For internal use only
313333H9PMFB
  • Multi-Function Button and power-on key
  • UART RX_IND, active-high (used by host MCU to wake up the Bluetooth system)
—3434—PLED3LED driver 3
333535G9PLED2LED driver 2
323636F9PLED1LED driver 1
—3737—PP3_7Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • UART TX_IND, active-low (used by Bluetooth system to wake-up the host MCU)
—3838—PP3_5

Configurable control or indication pin (Internally pulled-up, if configured as an input)

343939H7I/OP0_0Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • Slide switch detector, active-high
354040H8I/OP0_3Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • REV key (default), active-low
  • Buzzer signal output
  • Out_Ind_2
  • Class 1 Rx control signal of external RF T/R switch, active-high
364141—I/OEAN

For IS2062GM/64GM (Flash variant):

External address-bus negative System configuration pin along with the P2_0 and P2_4 pins can be used to set the SoC in any one of the following three modes:
  • Application mode (for normal operation)
  • Test mode (to change EEPROM values), and
  • Write Flash mode (to load a new firmware into the SoC), see Table 6-1

For IS2064S/B (ROM variant): Do not connect for this pin

—4242—PAVDD_USBUSB power input; connect to LDO31_VO pin
—4343—I/ODMDifferential data-minus USB
—4444—I/ODPDifferential data-plus USB
374545E9PCLDO_O1.2V core LDO output for internal use only. Connect to GND through a 1 μF capacitor
384646D9PPMIC_IN1.8V power input for internal blocks; connect to BK_O
394747C9PRFLDO_O1.28V RF LDO output for internal use only. Connect to GND through a 1 μF capacitor
404848D8PVBGBandgap output reference for decoupling interference, connect to GND through a 1 μF capacitor
414949C8PULPC_VSUSULPC 1.2V output power, maximum loading 1 mA, connect to GND through a 1 μF capacitor
425050B9IXO_N16 MHz crystal input negative
435151A9IXO_P16 MHz crystal input positive
445252A8PVCC_RFRF power input (1.28V) for both synthesizer and Tx/Rx block, connect to RFLDO_O
455353A7I/ORTX/ RF_RTXRF path (transmit/receive)
—5454—I/OP3_1Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • REV key when Class 1 RF (default), active-low
—5555—I/OP3_3Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • FWD key when Class 1 RF (default), active-low
—5656—I/OP3_6Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • Master/Slave mode control
465757G8I/OP0_2Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • Play/Pause key (default)
475858D5I/OP2_0

For IS2062GM/64GM (Flash variant):

External address-bus negative System configuration pin along with the P2_4 and EAN pins can be used to set the SoC in any one of the following three modes:
  • Application mode (for normal operation)
  • Test mode (to change EEPROM values), and
  • Write Flash mode (to load a new firmware into the SoC), see Table 6-1

For IS2064S/B (ROM variant): Do not connect for this pin

485959F8I/OP2_7Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • Volume up key (default), active-low
496060E8I/OP3_0Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • Auxiliary input detector, active-low
—6161—I/OTFS0I2S interface: left/right clock
506262B8I/OP0_5Configurable control or indication pin (Internally pulled-up, if configured as an input)
  • Volume down key (default), active-low
516363B2PVDD_IOI/O power supply input (3V to 3.6V); connect to LDO31_VO pin, connect to GND through a 1 μF (X5R/X7R) capacitor
—6464B7I/ODR0I2S interface: digital left/right data
—6565B6I/ORFS0I2S interface: left/right clock
—6666B5I/OSCLK0I2S interface: bit clock
—6767B4I/ODT0I2S interface: digital left/right data
5268—A5OAOHPRRight-channel, analog headphone output
57-6469-8369-83—PEPExposed pads, Used as ground (GND) pins
———A6, E4, E5, E6, F5PGNDGround reference
Note: All I/O pins are configured using UI tool, a Windows® based utility.