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19.14.5 TMRxCLK Timer Clock Source
Selection Register Name: TMRxCLK Offset: 0x211,0x217,0x21D
Bit 7 6 5 4 3 2 1 0 CS[4:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0
Bits 4:0 – CS[4:0] Timer Clock Source Selection
bits
Table 19-4. Timer Clock Sources CS Clock Source Timer1 Timer3 Timer5 11111-10001Reserved Reserved Reserved 10000CLC4_out CLC4_out CLC4_out 01111CLC3_out CLC3_out CLC3_out 01110CLC2_out CLC2_out CLC2_out 01101CLC1_out CLC1_out CLC1_out 01100Timer5 overflow
output Timer5 overflow
output Reserved 01011Timer3 overflow
output Reserved Timer3 overflow
output 01010Reserved Timer1 overflow
output Timer1 overflow
output 01001Timer0 overflow
output Timer0 overflow
output Timer0 overflow
output 01000CLKR
output CLKR
output CLKR
output 00111SOSC SOSC SOSC 00110MFINTOSC (32
kHz) MFINTOSC (32
kHz) MFINTOSC (32
kHz) 00101MFINTOSC (500
kHz) MFINTOSC (500
kHz) MFINTOSC (500
kHz) 00100LFINTOSC LFINTOSC LFINTOSC 00011HFINTOSC HFINTOSC HFINTOSC 00010FOSC FOSC FOSC 00001FOSC /4 FOSC /4 FOSC /4 00000T1CKIPPS T3CKIPPS T5CKIPPS
Reset States: POR/BOR = 00000 All Other Resets = uuuuu
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