28.6.5 TXxSTA
Transmit Status and Control Register
| Name: | TXxSTA |
| Offset: | 0x011E |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSRC | TX9 | TXEN | SYNC | SENDB | BRGH | TRMT | TX9D | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | RO | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
Bit 7 – CSRC Clock Source Select bit
Bit 6 – TX9 9-bit Transmit Enable bit
| Value | Description |
|---|---|
1 |
Selects 9-bit transmission |
0 |
Selects 8-bit transmission |
Bit 5 – TXEN Transmit Enable bit
Enables transmitter(1)
| Value | Description |
|---|---|
1 |
Transmit enabled |
0 |
Transmit disabled |
Bit 4 – SYNC EUSART Mode Select bit
| Value | Description |
|---|---|
1 |
Synchronous mode |
0 |
Asynchronous mode |
Bit 3 – SENDB Send Break Character bit
Bit 2 – BRGH High Baud Rate Select bit
Bit 1 – TRMT Transmit Shift Register (TSR) Status bit
| Value | Description |
|---|---|
1 |
TSR is empty |
0 |
TSR is not empty |
Bit 0 – TX9D Ninth bit of Transmit Data
Can be address/data bit or a parity bit.