23.8.1 Control A
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x80 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ONDEMAND | RUNSTDBY | FREERUN | ENABLE | SWRST | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 0 | 0 | 0 |
Bit 7 – ONDEMAND On Demand Control
During Sleep mode, the On Demand mode causes the FREQM clocks to be running when a measurement is requested by a peripheral or if free running operation mode is enabled. If there is no peripheral requesting the FREQM measurement, the module will not request any clock.
This bit is enable-protected.
| Value | Description |
|---|---|
| 0 | The FREQM is always requesting the clocks when CTRLA.ENABLE is set. |
| 1 | The FREQM is requesting the clocks only when a peripheral is requesting a measurement, or if free running mode is enabled. |
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the FREQM clocks will be requested during Standby S leep mode.
This bit is enable-protected.
| Value | Description |
|---|---|
| 0 | The FREQM clocks are not requested during Standby Sleep mode. If CTRLA.ONDEMAND = 1, the FREQM will request the clocks only if a measurement is requested. If CTRLA.ONDEMAND = 0, the FREQM clocks will be requested as long as CTRLA.ENABLE is set. |
| 1 | The FREQM clocks are requested in standby sleep mode. If CTRLA.ONDEMAND = 1, the FREQM will request the clocks only if a measurement is requested. If CTRLA.ONDEMAND = 0, the FREQM clocks will be requested as long as CTRLA.ENABLE is set. |
Bit 2 – FREERUN Free Running Mode
This bit controls the free running operation mode.
This bit is enable-protected.
| Value | Description |
|---|---|
| 0 | The free running operating mode is disabled. |
| 1 | The free running operating mode is enabled. |
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not enable-protected.
| Value | Description |
|---|---|
| 0 | The peripheral is disabled. |
| 1 | The peripheral is enabled. |
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the FREQM to their initial state, and the FREQM will be disabled. Writing a '1' to this bit will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.
This bit is not enable-protected.
- When the CTRLA.SWRST is written, the user should poll SYNCB.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.
| Value | Description |
|---|---|
| 0 | There is no ongoing Reset operation. |
| 1 | The Reset operation is ongoing. |