3.1.1 Transmit

The following IPs form the transmit part of the design:

  1. DATA_GENERATOR— This block has a PRBS generator and a waveform generator. The PRBS generator generates PRBS7, PRBS15, PRBS23, and PRBS31 patterns. An error insertion mode implemented in the PRBS generator, inserts an error into the PRBS sequence. The waveform generator generates sine, sawtooth, triangle, and square waveforms. The data generator feeds the 64-bit test pattern to the JESD204BTX core, which then transmits data to the transceiver.
  2. CoreJESD204BTX— This IP is the transmitter interface of the JEDEC JESD204B standard. For the SMA-based loopback design, the Core Configuration of this IP core is as follows:
    • Encoder: Removed
    • Data Width: 32
    • Serdes Mode: 1
    • Scrambling: Disabled
    • Device Subclass version: Subclass0
    • JESD204 version: JESD204B
    • Number of Lanes:1
    • Number of octets per frame: 2
    • Number of frames for multi-frame: 9
    • Number of multi-frames in ILA sequence: 4

      The Link Configuration of CoreJESD204BTX is as follows:

    • Number of converters per device: 2
    • Converter resolution: 16
    • Total Number of bits per sample: 16
    • Number of samples per converter per frame cycle: 1

    For more information about CoreJESD204BTX, see CoreJESD204BTX Handbook from Libero SoC catalog.

  3. ERR_GEN_0— This block generates link errors by sending random data between CoreJESD204BTX and PF_XCVR, when the link error generation is selected on the GUI.
  4. DATA_HANDLE_0— This block receives the input data selection and link or data error generation information from the GUI. Also, the block sends the data output received from the CoreJESD204BRX core and the data or link status error to the GUI for viewing.
  5. PF_XCVR_ERM— This is a hard IP block that supports high-speed data rates ranging from 250 Mbps to 12.5 Gbps. The following points summarize the configuration of the transceiver interface:
  • For the SMA loopback design, the transceiver block (PF_XCVR) is configured in 8b10b mode with a CDR reference clock of 156.25 MHz and data-rate of 6.25 Gbps. XCVR configuration settings are as follows:
    • Number of Lanes: 1; Enhanced receiver management: Enabled; Receiver calibration: None (CDR)
    • Transceiver data-rate: 6.25 Gbps; TX clock division factor: 1; TX PPLL base data-rate: 6.25 Gbps; TX PLL bit lock frequency: 3.125 Gbps
    • CDR Lock Mode: Lock to data; CDR reference clock source: Dedicated; CDR reference clock frequency: 156.25 MHz
    • PCS-Fabric interface width: 32-bit; 8b/10b Encoding/Decoding: Enabled
    • FPGA interface frequency: 156.25 MHz
  • For PCB loopback demo, the transceiver block (PF_XCVR) is configured for two lanes in 8b10b mode with a CDR reference clock of 125 MHz and data-rate of 5Gbps.
  • The PolarFire transmit PLL (PF_TX_PLL) send the reference clock feed to the transceiver. The dedicated reference clock (PF_XCVR_REF_CLK) drives the PF_TX_PLL to generate the desired output bit clock for the 6.25 Gbps or 5 Gbps data-rate.