1.2.2 I/O Glitch During Power-Down

I/O glitches can occur in some power-down sequences, and they can be ignored if good design practices are used. If the glitch on the I/Os during power-down of the FPGA cannot be ignored, the following might be used to mitigate the I/O glitch:

1. Add a 1 KΩ resistor to ground on all critical signal outputs such as clocks and resets and other glitch sensitive I/Os.
2. If possible, place the device in F*F mode prior to power-down.