1.2.1 I/O Glitch During Power-Up

I/O Glitches can occur in some power-up sequences, and they can be ignored if good design practices are used.

To mitigate the I/O glitch:
  1. Use any one of the following power-up sequence:
    1. Ensure VDD/VDDIOx powers-up before VPP (VDD/VDDIOx → VPP). During this time, DEVRST_N should also be de-asserted along with VPP.
    2. Assert DEVRST_N (Keep signal Low) until all the power rails are up. Only after all power rails are up de-assert DEVRST_N.
  2. If power sequencing is not possible, add a 10 KΩ resistor to ground on all critical signal outputs like clocks and resets.