1.7.3 SerDes Reference Clock Requirements

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The selection of the reference clock source or clock oscillator is driven by many parameters such as frequency range, output voltage swing, jitter (deterministic, random, and peak-to-peak), rise and fall times, supply voltage and current, noise specification, duty cycle and duty cycle tolerance, and frequency stability.

For SerDes reference clock pins, the internal ODT option must be enabled, and therefore, external termination is not required.

Following are the requirements for the SerDes reference clock:

Must be within the range of 100 MHz to 160 MHz.
Must be within the tolerance range of the I/O standard.
The input clock for PCIe is typically a 100 MHz reference clock provided by the host slot for an end point device through the PCIe connector of the motherboard. If two components connected through the PCIe bus use the same 100 MHz clock source, it is called common clock mode. In any other case, the PCIe device is in separated clock mode where one component either does not use a 100 MHz reference clock or uses a 100 MHz reference clock that does not have the same source and phase as the one used by the connected component.

See the PCI Express Base specification Rev 2.1 for detailed PHY specifications. Also see the PCIe Addin Card Electro-Mechanical (CEM) specifications.