51.12.34 SDMMC Capabilities 0 Register
- The reset values match the capabilities of the MPU alone. The user should adjust the capability registers so that they also match board design. Modify preset values only if the Capabilities Write Enable (CAPWREN) bit is set to 1 in SDMMC_CACR.
- The SRSUP, SDMASUP, HSSUP, ADMA2SUP, ED8SUP and MAXBLKL bits are read-only.
| Instance | Reset Value |
|---|---|
| SDMMC0 | 0x27EC0C8C |
| SDMMC1 | 0x27E80C8C |
| Name: | SDMMC_CA0R |
| Offset: | 0x40 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SLTYPE[1:0] | ASINTSUP | SB64SUP | V18VSUP | V30VSUP | V33VSUP | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | |||||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SRSUP | SDMASUP | HSSUP | ADMA2SUP | ED8SUP | MAXBLKL[1:0] | ||||
| Access | R | R | R | R | R | R | R | ||
| Reset | |||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BASECLKF[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TEOCLKU | TEOCLKF[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | |||||||||
Bits 31:30 – SLTYPE[1:0] Slot Type
This field indicates usage of a slot by a specific system. An SDMMC control register set is defined per slot.
Embedded Slot for One Device means that only one nonremovable device is connected to a bus slot.
The Standard Host Driver controls a removable card (SLTYPE = 0) or one embedded device (SLTYPE = 1) connected to an SD bus slot.
| Value | Name | Description |
|---|---|---|
| 0 | REMOVABLECARD | Removable Card Slot |
| 1 | EMBEDDED | Embedded Slot for One Device |
| 2 | – | Reserved |
| 3 | – | Reserved |
Bit 29 – ASINTSUP Asynchronous Interrupt Support
See section “Asynchronous Interrupt” in the “SDIO Simplified Specification V3.00” .
| Value | Description |
|---|---|
| 0 | Asynchronous interrupt not supported |
| 1 | Asynchronous interrupt supported |
Bit 28 – SB64SUP 64-Bit System Bus Support
Reading this bit to 1 means that the SDMMC supports the 64-bit Address Descriptor mode and is connected to the 64-bit address system bus.
| Value | Description |
|---|---|
| 0 | 64-bit address bus not supported |
| 1 | 64-bit address bus supported |
Bit 26 – V18VSUP Voltage Support 1.8V
| Value | Description |
|---|---|
| 0 | 1.8V voltage supply not supported |
| 1 | 1.8V voltage supply supported |
Bit 25 – V30VSUP Voltage Support 3.0V
| Value | Description |
|---|---|
| 0 | 3.0V voltage supply not supported |
| 1 | 3.0V voltage supply supported |
Bit 24 – V33VSUP Voltage Support 3.3V
| Value | Description |
|---|---|
| 0 | 3.3V voltage supply not supported |
| 1 | 3.3V voltage supply supported |
Bit 23 – SRSUP Suspend/Resume Support
This bit indicates whether the SDMMC supports the Suspend/Resume functionality. If this bit is set to 0, the user does not issue either Suspend or Resume commands because the Suspend and Resume mechanism (see “Suspend and Resume Mechanism” in the “SD Host Controller Simplified Specification V3.00” ) is not supported.
| Value | Description |
|---|---|
| 0 | Suspend/Resume not supported |
| 1 | Suspend/Resume supported |
Bit 22 – SDMASUP SDMA Support
This bit indicates whether the SDMMC is capable of using SDMA to transfer data between system memory and the SDMMC directly.
| Value | Description |
|---|---|
| 0 | SDMA not supported |
| 1 | SDMA supported |
Bit 21 – HSSUP High Speed Support
This bit indicates whether the SDMMC and the system support High Speed mode and they can supply SDCLK frequency from 25 MHz to 50 MHz.
| Value | Description |
|---|---|
| 0 | High Speed not supported |
| 1 | High Speed supported |
Bit 19 – ADMA2SUP ADMA2 Support
This bit indicates whether the SDMMC is capable of using ADMA2.
| Value | Description |
|---|---|
| 0 | ADMA2 not supported |
| 1 | ADMA2 supported |
Bit 18 – ED8SUP 8-Bit Support for Embedded Device
This bit indicates whether the SDMMC is capable of using the 8-bit Bus Width mode.
| Value | Description |
|---|---|
| 0 | 8-bit bus width not supported |
| 1 | 8-bit bus width supported |
Bits 17:16 – MAXBLKL[1:0] Max Block Length
This field indicates the maximum block size that the user can read and write to the buffer in the SDMMC. Three sizes can be defined, as shown below. It is noted that the transfer block length is always 512 bytes for SD Memory Cards regardless of this field.
| Value | Name | Description |
|---|---|---|
| 0 | 512 | 512 bytes |
| 1 | 1024 | 1024 bytes |
| 2 | 2048 | 2048 bytes |
| 3 | NONE | Reserved |
Bits 15:8 – BASECLKF[7:0] Base Clock Frequency
This value indicates the frequency of the base clock (BASECLK). The user uses this value to calculate the clock divider value (see SDCLK Frequency Select (SDCLKFSEL) in SDMMC_CCR).
If this field is set to 0, the user must get the information via another method.
Bit 7 – TEOCLKU Timeout Clock Unit
This bit shows the unit of the base clock frequency used to detect Data Timeout Error.
| Value | Description |
|---|---|
| 0 | KHz |
| 1 | MHz |
Bits 5:0 – TEOCLKF[5:0] Timeout Clock Frequency
This bit shows the timeout clock frequency (TEOCLK) used to detect Data Timeout Error.
If this field is set to 0, the user must get the information via another method.
The Timeout Clock Unit (TEOCLKU) defines the unit of this field’s value.
– TEOCLKU = 0:
– TEOCLKU = 1: