51.12.54 SDMMC Retuning Interrupt Status Register
Name: | SDMMC_RTISTR |
Offset: | 0x21C |
Reset: | 0x00 |
Property: | Read/Write |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TEVT | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit 0 – TEVT Retuning Timer Event
This bit is set to 1 when the retuning timer count is elapsed if SDMMC_RTISTER.TEVT is set to 1. An interrupt is generated if SDMMC_RTISIER.TEVT is set to 1.
Writing this bit to 1 clears the bit.
Value | Description |
---|---|
0 |
No retuning timer event. |
1 |
Retuning timer event. |