49.15 SPI Comparison Register
This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register.
| Name: | SPI_CMPR |
| Offset: | 0x48 |
| Reset: | 0x0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| VAL2[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VAL2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VAL1[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VAL1[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:16 – VAL2[15:0] Second Comparison Value for Received Character
| Value | Description |
|---|---|
| 0–65535 |
The received character must be lower or equal to the value of VAL2 and higher or equal to VAL1 to set CMP flag in SPI_CSR. If asynchronous partial wake-up is enabled in PMC_SLPWK_ER, the SPI requests a system wake-up if condition is met. |
Bits 15:0 – VAL1[15:0] First Comparison Value for Received Character
| Value | Description |
|---|---|
| 0–65535 |
The received character must be higher or equal to the value of VAL1 and lower or equal to VAL2 to set CMP flag in SPI_SR. If asynchronous partial wake-up is enabled in PMC_SLPWK_ER, the SPI requests a system wake-up if the condition is met. |