2.2 Clocking Structure

In the demo design, there are two clock domains—the on-board 50 MHz oscillator and the on-board ZL30364 clock generation hardware.

  • On-board 50 MHz oscillator: This oscillator drives the PLL that generates an 83.33 MHz clock for the Mi-V soft processor and peripherals. The Mi-V soft processor can operate at maximum 120 MHz. In this design, the Mi-V processor runs at 83.33 MHz.
  • On-board ZL 30364 clock generation hardware: This hardware generates the reference clocks for the VSC PHY and the IOD CDR fabric module.

The following figure shows the clocking structure of the demo design.

Figure 2-17. Clocking Structure