2.1 Design Implementation

The following figure shows the top-level Libero implementation of the demo design. The libero project implementation is the same for both webserver and IAP using TFTP but the application firmware is different.

Figure 2-2. Top-Level Libero Implementation

The following table lists the important I/O signals of the design.

Table 2-1. I/O Signals
SignalDirectionDescription
RX_P, RX_NInputIOD CDR receive signals connected to the VSC PHY transmit data signals.
REFCLK_N, REFCLK_PInputThe 125 MHz input clock received from the on-board ZL30364 and fed to NWC_PLL_0.
RESET_NInputMi-V Reset. Asserted by pressing the on-board K22 push button.
REF_CLK_0InputThe 50 MHz input clock received from the on-board 50 MHz oscillator and fed to PF_CCC_0.
TCK, TDI, TMS, and TRSTBInputJTAG signals interfacing the soft processor for debugging.
TDOOutput
TX_P, TX_NOutputIOD CDR transmit signals connected to the VSC PHY receive data signals.
LINK_OKOutputLink status indicator. Provides the link up or down status with the on-board PHY. This signal is mapped to the on-board LED7. The LED ON state indicates that the link is up.
PHY_RSTOutputReset signal to the on-board VSC8575 PHY.
PHY_MDCOutputThe MDIO clock fed to the on-board VSC8575 PHY.
PHY_MDIOOutputManagement Data I/O interface for accessing the on-board VSC8575 PHY registers.
coma_modeOutputSignal held Low (connected to ground) to keep the VSC PHY fully active when it is out of Reset.
REF_CLK_SELOutputReference clock speed pin of the VSC PHY. Held High for selecting the 
125 MHz reference clock speed.
RD_BC_ERROROutputCoreTSE receive error signal. Indicates the receive code group error. This signal is synchronous to RX_CLK_R and mapped to the on-board LED4. The LED ON condition indicates an error in the received code group.
SPISCLKO, SPISS, and SPISDOOutputSPI controller signals to interface with the ZL30364 clock generation hardware.
SPISDIInput