10.4 Interfacing with an I²S Interface
The SAMA7G54 SOM Series embeds two Inter-IC Sound Multi-Channel Controllers (I2SMCC0 and I2SMCC1) which provide an up to 11-wire, bidirectional, synchronous, digital audio link to external audio devices.
The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and supports a Time Division Multiplexed (TDM) interface with external multi-channel audio codecs.
The I2SMCC consists of a receiver, a transmitter and a common clock generator that can be enabled separately to provide Host, Client or Controller modes with receiver and/or transmitter active.
In Host mode, the I2SMCC can produce a 16 fs to 1024 fs host clock that provides an over-sampling clock to an external audio codec or Digital Signal Processor (DSP).
| Interface Instance | IO Set | Pin No. | Pin Name | Function |
|---|---|---|---|---|
| I2SMCC0 | 2 | 21 | PD13 | I²S Serial Clock (I2S_CK) |
| 22 | PD14 | I²S Bus Clock (I2S_MCK) | ||
| 119 | PD15 | I²S Word Select (I2S_WS) | ||
| 24 | PD16 | I²S Serial Data 0 Output (I2S_DOUT0) | ||
| 26 | PD17 | I²S Serial Data 1 Output (I2S_DOUT1) | ||
| 111 | PD18 | I²S Serial Data 2 Output (I2S_DOUT2) | ||
| 110 | PD19 | I²S Serial Data 3 Output (I2S_DOUT3) | ||
| I2SMCC1 | 1 | 89 | PC11 | I²S Serial Clock (I2S_CK) |
| 91 | PC13 | I²S Bus Clock (I2S_MCK) | ||
| 90 | PC12 | I²S Word Select (I2S_WS) | ||
| 92 | PC14 | I²S Serial Data 0 Output (I2S_DOUT0) | ||
| 93 | PC15 | I²S Serial Data 1 Output (I2S_DOUT1) | ||
| 99 | PC16 | I²S Serial Data 2 Output (I2S_DOUT2) | ||
| 100 | PC17 | I²S Serial Data 3 Output (I2S_DOUT3) | ||
| 101 | PC18 | I²S Serial Data 0 Input (I2S_DIN0) | ||
| 102 | PC19 | I²S Serial Data 1 Input (I2S_DIN1) | ||
| 103 | PC20 | I²S Serial Data 2 Input (I2S_DIN2) | ||
| I2SMCC1 | 2 | 35 | PD28 | I²S Serial Clock (I2S_CK) |
| 31 | PD30 | I²S Bus Clock (I2S_MCK) | ||
| 33 | PD29 | I²S Word Select (I2S_WS) | ||
| 34 | PD31 | I²S Serial Data 0 Output (I2S_DOUT0) | ||
| 44 | PE0 | I²S Serial Data 1 Output (I2S_DOUT1) | ||
| 45 | PE1 | I²S Serial Data 2 Output (I2S_DOUT2) | ||
| 47 | PE2 | I²S Serial Data 3 Output (I2S_DOUT3) | ||
| 46 | PE3 | I²S Serial Data 0 Input (I2S_DIN0) | ||
| 48 | PE4 | I²S Serial Data 1 Input (I2S_DIN1) | ||
| 48 | PE5 | I²S Serial Data 2 Input (I2S_DIN2) | ||
| 50 | PE6 | I²S Serial Data 3 Input (I2S_DIN3) |