10.6 Interfacing with an Image Sensor
The SAMA7G54 SOM Series embeds an Image Subsystem connecting to an image sensor through an RGB parallel interface (ISC interface) or through a dual-lane high-speed MIPI interface (CSI interface).
The Image Sensor Controller (ISC) system manages incoming data from a parallel sensor. The ISC supports an 8- to 12-bit interface camera sensor with a resolution up to 3264x2464.
| Interface Instance | IO Set | Pin No. | Pin Name | Function |
|---|---|---|---|---|
| ISC | 1 | 186 | PA27 | Image Sensor Pixel clock |
| 181 | PA25 | Image Sensor Vertical Synchronization | ||
| 183 | PA24 | Image Sensor Horizontal Synchronization | ||
| 180 | PA15 | Image Sensor Main clock | ||
| 185 | PA26 | Field Identification Signal | ||
| 179 | PA16 | Image Sensor Data 0 Line | ||
| 174 | PA17 | Image Sensor Data 1 Line | ||
| 177 | PA18 | Image Sensor Data 2 Line | ||
| 182 | PA19 | Image Sensor Data 3 Line | ||
| 175 | PA20 | Image Sensor Data 4 Line | ||
| 178 | PA21 | Image Sensor Data 5 Line | ||
| 176 | PA22 | Image Sensor Data 6 Line | ||
| 184 | PA23 | Image Sensor Data 7 Line | ||
| 187 | PA28 | Image Sensor Data 8 Line | ||
| 188 | PA29 | Image Sensor Data 9 Line | ||
| 3 | PA30 | Image Sensor Data 10 Line | ||
| 4 | PA31 | Image Sensor Data 11 Line |
The Camera Serial Interface (CSI) receives data from a CSI-2-compliant camera sensor. A D-PHY configured as a client (RX) acts as the physical layer.
The CSI implements the MIPI CSI-2 protocol specification. The CSI-2 link protocol specification is part of communication protocols defined by MIPI Alliance standards intended for mobile system chip-to-chip communications. The CSI-2 specification applies to image application processor communication in cameras.
For more information about the Camera Serial Interface features, refer to the SAMA7G5 Series SiP data sheet (see Reference Documents).
| Interface Instance | Pin No. | Pin Name | Function |
|---|---|---|---|
| MIPI CSI | 168 | MIPI_D0_N | Negative D-PHY differential data line receiver, Lane 0 |
| 167 | MIPI_D0_P | Positive D-PHY differential data line receiver, Lane 0 | |
| 166 | MIPI_D1_N | Negative D-PHY differential data line receiver, Lane 1 | |
| 165 | MIPI_D1_P | Positive D-PHY differential data line receiver, Lane 1 | |
| 164 | MIPI_CK_N | Negative D-PHY differential clock line receiver | |
| 163 | MIPI_CK_P | Positive D-PHY differential clock line receiver |