21.6.3.3 Enum system_clock_dfll_chill_cycle

DFLL chill cycle behavior modes of the DFLL module. A chill cycle is a period of time when the DFLL output frequency is not measured by the unit, to allow the output to stabilize after a change in the input clock source.

Table 21-59. Members
Enum valueDescription

SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE

Enable a chill cycle, where the DFLL output frequency is not measured

SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE

Disable a chill cycle, where the DFLL output frequency is not measured