High-Performance 32-bit MCUs with Floating-Point Unit and High-Speed ADCs


Operating Conditions 3.0V to 3.6V: -40°C to +85°C, DC to 200 MHz 3.0V to 3.6V: -40°C to +125°C, DC to 200 MHz High-Performance 32-bit CPU 32-bit Comprehensive Instruction Set for Optimized Speed and Program Code Size: Non-paged linear Data/Flash 24-bit addressing space 16-bit/32-bit instructions for optimized code size and performance 32-bit Wide Data Paths Single and Double Precision Floating-Point Unit (FPU) Coprocessor 2 Kbyte Instruction Cache Sixteen 32-bit Working Registers Dual 72-bit Accumulators Supporting 32-bit and 16-bit Fixed-Point DSP Operations Eight Level Deep Working Register Contexts Eight Level Deep Accumulator Register Contexts Eight Level Deep Floating Point Register Contexts Memory Features Up to 128 Kbytes of Program Flash Memory: 10,000 erase/write cycle endurance 20 years minimum data retention Self-programmable under software control Programmable code protection Flash Error Correcting Code (ECC) Programmable OTP regions Entire Flash OTP by ICSP™ write inhibit 64 x128-bit OTP area Up to 16 Kbytes of RAM Memory: 6-channel hardware Direct Memory Access (DMA) module RAM Error Correcting Code (ECC) RAM Memory Built-In Self-Test (MBIST)	Controller Features High-Current Sink/Source Capable I/Os Programmable Weak Pull-Up and Pull-Down Resistors Programmable Open-Drain Outputs Edge or Level Change Notification Interrupt on I/O pins Peripheral Pin Select (PPS) Remappable Pins to Reduce Board Layout Complexity Multiple Interrupt Vectors with Individual Programmable Priority Five External Interrupt Pins Selectable Oscillator Options Including: 8 MHz, 1% at 0ºC-85ºC Internal Fast RC (FRC) oscillator 8 MHz, 2% Internal Backup Fast RC (BFRC) oscillator with 32 kHz divided output High-speed crystal resonator oscillator or external clock Two 1.6 GHz PLLs for Peripherals which can be clocked from the FRC or a Crystal Oscillator Reference Clock Output (REFO) Low-Power Modes (Sleep and Idle) Power-On Reset and Brown-Out Reset High-Speed PWM Four PWM Generators (Four Pairs, Eight Outputs) Up to 2.5 ns PWM Resolution Dead Time for Rising and Falling Edges Dead-Time Compensation Supports Lower Speed Operation PWM Support for: BLDC, PMSM, ACIM, SRM and Stepper Motors Fault and Current Limit Inputs Flexible Trigger Configuration for ADC Triggering


Two High-Speed Analog-to-Digital Converters 12-bit Resolution Up to 40 Msps Conversion Rate Up to 22 Analog Input Pins 20 Settings Channels. Each Channel: Supports Discrete Configuration Can be assigned to any analog input (I/O pin or internal signal) Can be set to a different sampling time Can be configured as single-ended or differential Conversion result can be formatted as unsigned or signed Conversion result can be left-aligned (fraction format) Has a separate 32-bit conversion result register Supports Four Sampling modes: Oversampling of multiple samples Integration of multiple samples Window (multiple samples accumulated when the gate signal is active) Single Conversion All channels have a digital comparator to detect configurable thresholds Three channels support second result accumulator to implement second order filters Band Gap Reference and Temperature Sensor Diode Inputs Analog Features Three 5 nS Analog Comparators with 12-bit Pulse Density Modulation DACs: Input multiplexing Slope compensation One DAC output buffer Three Rail-to-Rail 100 MHz Operational Amplifiers with: 100 V/µS slew rate 1 mV offset (typical) User calibration of input offset voltage Four 10 µA Constant Sources + Four Programmable Sources Peripheral Features Three 4-Wire SPI Modules: 4-byte FIFO Variable data width I²S mode Two I²C modules: Independent Host and Client Logic Supports 100 kHz, 400 kHz and 1 MHz Bus Specifications 7-bit and 10-bit Device Addresses Supports IPMI Standard, SMBus and PMBus Three Protocol UARTs with 8-Character RX/TX FIFOs Automated UART Handling Support for: LIN 2.2 Digital Multiplex 512 (DMX) Smart Card (ISO 7816) IrDA^®	Security Module Secure Boot Secure Debug Immutable Root of Trust (IRT) Code Protect ICSP Program/Erase Disable Firmware IP Protection Flash Write Protection Safety Features Windowed Watchdog Timer (WDT) Deadman Timer (DMT) Four I/O Integrity Monitors (IOIM) Fail-Safe Clock Monitor (FSCM) with Automatic Switchover to Backup Clock Source Flash Error Correcting Code (NVM ECC) RAM Error Correcting Code (RAM ECC) RAM Memory Built-In Self-Test (MBIST) 32-bit Cyclic Redundancy Check (CRC) Module Entire Flash OTP by ICSP™ Write Inhibit Capless Internal Voltage Regulator Virtual PPS Pins for Redundancy and Monitoring Temperature Sensor Diode Functional Safety Functional Safety Readiness – ISO 26262/IEC 61508/IEC 60730 To learn about the Functional Safety Readiness of this device family and various Functional Safety standards an application can target using this device family, visit www.microchip.com/PIC32-Functional-Safety Qualification AEC-Q100 REV H: Grade 1: -40°C to +125°C Programming and Debug Features Three Programming and Debugging Interfaces: Two-wire ICSP™ interface with non-intrusive access and real-time data exchange with application Five Program Addresses and Five Full-Featured Breakpoints JTAG/IEEE Standard 1149.2 Compatible Boundary Scan