13 Interrupt Controller

The PIC32AK1216GC41064 family interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to its CPU. The core supports a prioritized interrupt and trap exception scheme.

The interrupt controller has the following features:

  • Interrupt Vector Table (IVT) for User Memory
  • Reset Vector (Not Part of IVT)
  • 8 Processor Traps
  • 4 Generic Traps + 1 Software Trap
  • 7 User Selectable Priority Levels
  • A Unique Vector for Each Interrupt or Exception in Full IVT Mode
  • A Collapsed Vector for All Peripheral Interrupts
  • Fixed Priority Within a Specified User Priority Level
  • Software Can Generate Any Peripheral Interrupt
  • Relocatable IVT (via IVTBASE Register)
  • Support for Testability via INTTREG