38 Instruction Set Summary

The PIC32AK1216GC41064 family of devices supports modified Harvard architecture. For details of the 32-bit Comprehensive Instruction Set for the PIC32AK1216GC41064 device family, refer to the “PIC32A Programmer's Reference Manual”, which is available from the Microchip website (www.microchip.com).

The instruction set is highly orthogonal and is grouped into five basic categories:

Long word, word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations

Table 1 lists the general symbols used in describing the instructions.

The instruction set summary in Table 38-2 lists all the instructions, along with the status flags affected by each instruction.

Most long word, word or byte-oriented operations W register instructions (including barrel shift instructions) have three operands:

The first source operand, which is typically a register ‘Wb’ without any address modifier
The second source operand, which is typically a register ‘Ws’ with or without an address modifier
The destination of the result, which is typically a register ‘Wd’ with or without an address modifier

However, long word, word or byte-oriented operations file register instructions have two operands:

The file register specified by the value ‘f’
The destination, which could be either the file register ‘f’ or any W register

Most bit-oriented instructions (including simple rotate/shift instructions) have two operands:

The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’)
The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’)

The literal instructions that involve data movement can use some of the following operands:

A literal value to be loaded into a W register (specified by ‘k’)
The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or logical operations use some of the following operands:

The first source operand, which is a register ‘Wb’ without any address modifier
The second source operand, which is a literal value
The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier

The MAC class of DSP instructions can use some of the following operands:

The accumulator (A or B) to be used (required operand)
The W registers to be used as the two operands
The X and Y address space prefetch operations
The X and Y address space prefetch destinations
The accumulator write-back destination

The other DSP instructions do not involve any multiplication and can include:

The accumulator to be used (required)
The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier
The amount of shift specified by a W register ‘Wn’ or a literal value

The control instructions can use a program memory address.

Most single-word instructions are executed in a single instruction cycle unless a conditional test is true, the Program Counter is changed as a result of the instruction. In these cases, the execution takes multiple instruction cycles with the additional instruction cycle(s) executed as a NOP. Certain instructions that involve skipping over the subsequent instruction require extra cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction.

Note: For more details on the instruction set, refer to the “PIC32A Programmer's Reference Manual (DS70005540)” (www.microchip.com/).

Table 38-1. Symbols Used in Opcode Descriptions
Symbol⁽¹⁾	Description
`{ }`	Optional field or operation
`[text]`	The location addressed by text
`(text)`	The contents of text
`#text`	The literal defined by text
`{label:}`	Optional label name
`[n:m]`	Register bit field
`.l`	32-bit Long Word mode selection
`.b`	8-bit Byte mode selection
`.sl`	24-bit (literal) Word mode selection
`.V`	Destination data value select (MAXABW, MINABW and FLIMW)
`.w`	16-bit Word mode selection (default)
`AWB`	Accumulator write back destination address register
`bit3`	3-bit bit selection field (used in byte addressed instructions) (0:7)
`bit4`	4-bit bit selection field (used in word addressed instructions) (0:15)
C, N, OV, Z	ALU status bits: Carry, Digit Carry, Negative, Overflow, Zero
d	File register destination (W0, none)
`Expr`	Absolute address, label or expression (resolved by the linker)
`f`	File register address (0x0000:0xFFFF) or (0x00000:0xFFFFF) (addressable space varies depending upon instruction class)
`Fd`⁽²⁾	One of 32 FPU destination data registers (F0:F31) (Register Direct)
`Fs`⁽²⁾	One of 32 FPU source data registers (F0:F31) (Register Direct)
`FSR`, `FSRH`, `FCR`, `FEAR 1`⁽²⁾	FPU special (control & status) coprocessor registers (Register Direct)
`label`	Translates to a literal representing the location of the label name
`lit1`	1-bit unsigned literal (0:1)
`lit3`	3-bit unsigned literal (0:7)
`lit5`	5-bit unsigned literal (0:31)
`lit6`	6-bit unsigned literal (0:63)
`lit8`	8-bit unsigned literal (0:255)
`lit16`	16-bit unsigned literal (0:65535)
`lit24`	24-bit unsigned literal (0:1677215; LSb must be `0` if an address)
`lit32`	32-bit unsigned literal (0:4294967295)
`none`	Field does not require an entry and may be blank
`OA`, `OB`, `SA`, `SB`	DSC status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
`PC`	Program Counter
`Rdo`	Destination Working register
`Rnd`	Instruction rounding mode [E, Z, P, N]
`Rso`	Source Working register
`Slit6`	Signed 6-bit literal (-32:31)
`Slit7`	Signed 7-bit literal (-64:63)
`Slit8`	Signed 8-bit literal (-128:127)
`Slit20`	Signed 20-bit literal (-524288:524287)
`SR`	Status Register
`text1` ∈ `{text2`, `{text3,…}`	`text1` must be in the set of `text2`, `text3`, ...
v	Selects MULxxx operand data types
`Wb`	Base Working register
`Wd`	Destination Working register
`Wm`	One of 16 Working registers (W0:W15)
`Wn`	Both source and destination Working register (W0:W15)
`Wnd`	One of 16 destination Working registers
`Wns`	One of 16 source Working registers
`Wm * Wm`	Multiplicand and Multiplier Working register for Square instructions
`Wm * Wn`	Multiplicand and Multiplier W register for DSP instructions
`Ws`	Source Working register
`Wx`	X data space fetch address register for DSP instructions
`Wy`	Y data space fetch address register for DSP instructions
Note: The range of each symbol is instruction-dependent. Only applicable when the FPU coprocessor is present. Read and Read-Modify-Write (RMW) operations on non-CPU Special Function Registers require additional cycles when updating SFRs belonging to peripherals on different peripheral clock speeds. The bus speed should be taken into consideration on time sensitive writes.

Table 38-2. Instruction Set Overview
Base Instr #	Assembly Mnemonic	Assembly Syntax	Description	# of Words	# of Cycles⁽¹⁾	Status Flags Affected
1	ABS	ABS Fs, Fd	Absolute value of Fs (FPU Instr)	1	1	SUBO
2	ADD	ADD A	Add Accumulators	0.5	1	OA, SA, OB, SB
		ADD Rso,#Slit6, A	16-bit Signed Add to Accumulator	1	1	OA, SA, OB, SB
		ADD f,Wn	f = f + Wn	1	1	C, N, OV, Z
		ADD f,Wn,Wn	Wn = f + Wn	1	1	C, N, OV, Z
		ADD.l #lit5,Wn	Wn = Wn + lit5	0.5	1	C, N, OV, Z
		ADD #lit16,Wn	Wn = Wn + lit16	0.5/1	1	C, N, OV, Z
		ADD Wb,Ws,Wd	Wd = Wb + Ws	1	1	C, N, OV, Z
		ADD Wb,#lit7,Wd	Wd = Wb + lit7 (literal zero-extended)	1	1	C, N, OV, Z
		ADD Fb, Fs, Fd	Fd = Fb + Fs (FPU Instr)			SUBO, INX, UDF, OVF, INVAL
3	ADDC	ADDC f,Wn	f = f + Wn + (C)	1	1	C, N, OV, Z
		ADDC f,Wn,Wn	Wn = f + Wn + (C)	1	1	C, N, OV, Z
		ADDC #lit16,Wn	Wn = Wn + lit16 + (C)	1	1	C, N, OV, Z
		ADDC Wb,Ws,Wd	Wd = Wb + Ws + (C)	0.5/1	1	C, N, OV, Z
		ADDC Wb,#lit7,Wd	Wd = Wb + lit7 + (C)(literal zero-extended)	1	1	C, N, OV, Z
4	AND	AND f,Wn	f = f .AND. Wn	1	1	N, Z
		AND f,Wn,Wn	W0 = f .AND. Wn	1	1	N, Z
		AND #lit16,Wn	Wn = Wn .AND. lit16	1	1	N, Z
		AND Wb,Ws,Wd	Wd = Wb .AND. Ws	0.5/1	1	N, Z
		AND Wb,#lit7,Wd	Wd = Wb .AND. Lit7 (literal zero-extended)	1	1	N, Z
		AND1 Wb,#lit7,Wd	Wd = Wb .AND. Lit7 (literal zero-extended)	1	1	N, Z
		AND #lit16, FSR	FSR = FSR AND lit16 (FPU instr)	1	1	SUBO, HUGI, INX, UDF, OVF, DIV0, INVAL
		AND #lit16, FCR	FCR = FCR AND lit16 (FPU instr)	1	1	None
		AND #lit16, FEAR	FEAR = FEAR AND lit16 (FPU instr)	1	1	None
5	ASR	ASR f	f = Arithmetic Right Shift f by 1	1	1	N, Z
		ASR f,Wn	Wn = Arithmetic Right Shift f by 1	1	1	N, Z
		ASR Ws,Wd	Wd = Arithmetic Right Shift Ws by 1	0.5/1	1	N, Z
		ASR Ws,Wb,Wd	Wnd = Arithmetic Right Shift Ws by Wb	0.5/1	1	N, Z
		ASR Ws,lit5,Wd	Wnd = Arithmetic Right Shift Ws by lit5	0.5/1	1	N, Z
6	ASRM	ASRM Ws, #lit5, Wnd	Wnd = Arithmetic Right Shift Ws by lit5, then logically OR with next lsw	1	2	N, Z
6	ASRM	ASRM Ws, Wb, Wnd	Wnd = Arithmetic Right Shift Ws by Wb, then logically OR with next lsw	1	2	N, Z
7	BCLR	BCLR.b f,bit3	Bit Clear f	1	1	None
7	BCLR	BCLR Ws,bit4	Bit Clear Ws	0.5/1	1	None
8	BFEXT	BFEXT bit4,wid5,Ws,Wb	Bit Field Extract from Ws to Wb	1	1	None
8	BFEXT	BFEXT bit4,wid5,f,Wb	Bit Field Extract from f to Wb	2	2	None
9	BFINS	BFINS bit4,wid5,Wb,Ws	Bit Field Insert from Wb into Ws	1	1	None
		BFINS bit4,wid5,Wb,f	Bit Field Insert from Wb into f	2	2	None
		BFINS bit4,wid5,#lit8,Ws	Bit Field Insert lit8 into Ws	2	2	None
10	BOOTSWP	BOOTSWP	Swap the Active and Inactive Program Flash Space	1	2	None
11	BRA	BRA Label	Branch Unconditionally	1	1	None
		BRA Wn	Computed Branch	1	2	None
		BRA C,Label	Branch if Carry	1	1(2/3)	None
		BRA GE,Label	Branch if greater than or equal	1	1(2/3)	None
		BRA GEU,Label	Branch if unsigned greater than or equal	1	1(2/3)	None
		BRA GT,Label	Branch if greater than	1	1(2/3)	None
		BRA GTU,Label	Branch if unsigned greater than	1	1(2/3)	None
		BRA LE,Label	Branch if less than or equal	1	1(2/3)	None
		BRA LEU,Label	Branch if unsigned less than or equal	1	1(2/3)	None
		BRA LT,Label	Branch if less than	1	1(2/3)	None
		BRA LTU,Label	Branch if unsigned less than	1	1(2/3)	None
		BRA N,Label	Branch if Negative	1	1(2/3)	None
		BRA NC,Label	Branch if Not Carry	1	1(2/3)	None
		BRA NN,Label	Branch if Not Negative	1	1(2/3)	None
		BRA NOV,Label	Branch if Not Overflow	1	1(2/3)	None
		BRA NZ,Label	Branch if Not Zero	1	1(2/3)	None
		BRA Z,Label	Branch if Zero	1	1(2/3)	None
		BRA OA,Label	Branch if accumulator A overflow	1	1(2/3)	None
		BRA OB,Label	Branch if accumulator B overflow	1	1(2/3)	None
		BRA OV,Label	Branch if Overflow	1	1(2/3)	None
		BRA SA,Label	Branch if accumulator A saturated	1	1(2/3)	None
		BRA SB,Label	Branch if accumulator B saturated	1	1(2/3)	None
12	BREAK	BREAK	Stop User Code Execution	1	1	None
13	BSET	BSET.b f,bit3	Bit Set f	1	1	None
13	BSET	BSET Ws,bit4	Bit Set Ws	0.5/1	1	None
14	BSW	BSW.C Ws,Wb	Write C or Z bit to Ws<Wb>	1	1	None
14	BSW	BSW.Z Ws,Wb	Write C or Z bit to Ws<Wb>	0.5/1	1	None
15	BTG	BTG.b f,bit3	Bit Toggle f	1	1	None
15	BTG	BTG Ws,bit4	Bit Toggle Ws	0.5/1	1	None
16	BTSC		Not supported			N/A
17	BTSS		Not supported			N/A
18	BTST	BTST.b f,bit3	Bit Test f	1	1	Z
		BTST.C Ws,bit4	Bit Test Ws to C	0.5/1	1	C, Z
		BTST.Z Ws,bit4	Bit Test Ws to Z	1	1	Z
		BTST.C Ws,Wb	Bit Test Ws<Wb> to C	0.5/1	1	C, Z
		BTST.Z Ws,Wb	Bit Test Ws<Wb> to Z	1	1	Z
19	BTSTS	BTSTS.b f,bit3	Bit Test then Set f	1	1	Z
		BTSTS.C Ws,bit4	Bit Test Ws to C then Set	0.5/1	1	C, Z
		BTSTS.Z Ws,bit4	Bit Test Ws to Z then Set	1	1	Z
20	CALL	CALL Label	Call subroutine (label > ~ 16MB)	1	1	None
		CALL Label	Call subroutine (label < ~ 16MB)	2	2	None
		CALL Wns	Call indirect subroutine at address [W11]	1	2	None
21	CLR	CLR f	f = 0x0000 0000	1	1	None
		CLR Wd	Wd = 0x0000 0000	1	1	None
		CLR A	Clear Accumulator	0.5	1	None
21	CLRWDT	CLRWDT	Clear Watchdog Timer	0.5	1	WDTO, Sleep
22	COM	COM f	f = f	1	1	N, Z
		COM f,Wd	Wd = f	1	1	N, Z
		COM Ws,Wd	Wd = Ws	0.5/1	1	N, Z
23	CP	CP f,Ws	Compare f with Ws	1	1	C, N, OV, Z
		CP Ws,#lit13	Compare Ws with lit13 (literal zeroextended)	1	1	C, N, OV, Z
		CP Wb,#lit16	Compare Wb with lit16 (literal zeroextended)	1	1	C, N, OV, Z
		CP Wb, Ws	Compare Wb with Ws	0.5/1	1	C, N, OV, Z
24	CP0	CP0 f	Compare f with 0x0000 0000	1	1	C, N, OV, Z
24	CP0	CP0 Ws	Compare Ws with 0x0000 0000 (substitute CPLS Ws ,#0)	1	1	C, N, OV, Z
25	CPB	CPB f,Ws	Compare f with Ws, with borrow	1	1	C, N, OV, Z
		CP Wb,#lit13	Compare Wb with lit13, with borrow (literal zero-extended)	1	1	C, N, OV, Z
		CP Wb,#lit16	Compare Wb with lit16, with borrow (literal zero-extended)	1	1	C, N, OV, Z
		CPB Wb,Ws	Compare Borrow Wb with Ws	0.5/1	1	C, N, OV, Z
	CPSEQ		Not supported			N/A
	CPBEQ		Not supported			N/A
	CPSGT		Not supported			N/A
	CPBGT		Not supported			N/A
	CPSNE		Not supported			N/A
26	CTXTSWP	CTXTSWP #lit3	Swap to CPU register context defined by lit3	0.5	2	None
26	CTXTSWP	CTXTSWP Wn	Swap to CPU register context defined in Wn[2:0]	1	2	None
27	DAW		Not supported			N/A
28	DEC	DEC f	f = f -1	1	1	C, N, OV, Z
		DEC f,Wd	W5 = f -1	1	1	C, N, OV, Z
		DEC Ws,Wd	Wd = Ws - 1	1	1	C, N, OV, Z
29	DEC2	DEC2 f	f = f -2	1	1	C, N, OV, Z
		DEC2 f,Wd	W5 = f -2	1	1	C, N, OV, Z
		DEC2 Ws,Wd	Wd = Ws - 2	1	1	C, N, OV, Z
30	DISI		Not supported			N/A
31	DISICTL	DISICTL #lit3 {,Wd}	Disable interrupts at IPL <= lit3 Optionally save prior IPL threshold to Wd	1	1	None
31	DISICTL	DISICTL Wns {,Wd}	Disable interrupts at IPL <= Wns[2:0] Optionally save prior IPL threshold to Wd	1	1	None
32	DIVF	DIVF Wm/Wn	Interruptible Signed 16/16 or 32/16 Fractional Divide	1	1	C, N, OV, Z
33	DIVFL	DIVFL Wm/Wn	Interruptible Signed 32/32 Fractional Divide	1	1	C, N, OV, Z
34	DIVS	DIVS.w Wm/Wn	Interruptible Signed 16/16-bit Integer Divide	1	1	C, N, OV, Z
34	DIVS	DIVS.l Wm/Wn	Interruptible Signed 32/16-bit Integer Divide	1	1	C, N, OV, Z
35	DIVSL	DIVSL Wm/Wn	Interruptible Signed 32/32 Integer Divide	1	1	C, N, OV, Z
36	DIVU	DIVU.w Wm/Wn	Interruptible Unsigned 16/16-bit Integer Divide	1	1	C, N, OV, Z
36	DIVU	DIVU.l Wm/Wn	Interruptible Unsigned 32/16-bit Integer Divide	1	1	C, N, OV, Z
37	DIVUL	DIVUL Wm/Wn	Interruptible Unsigned 32/32 Integer Divide	1	1	C, N, OV, Z
38	DIV2		Not supported			N/A
39	DTB	DTB Wn,Label	Decrement Wn, then branch if not zero	1	1(2/3)	None
40	DO		Not supported			N/A
41	ED	ED Wxp * Wyp, A, AWB	Euclidean Distance	1	2	OA, SA, OB, SB
42	EDAC	EDAC Wxp * Wyp, A, AWB	Euclidean Distance Accumulate	1	2	OA, SA, OB, SB
43	EXCH	EXCH Wns,Wnd	Swap Wns with Wnd	1	2	None
44	FBCL	FBCL Ws,Wnd	Find Bit Change from Left (MSb) Side	1	1	C
45	FF1L	FF1L Ws,Wnd	Find First One from Left (MSb) Side	1	1	C
46	FF1R	FF1R Ws,Wnd	Find First One from Right (LSb) Side	1	1	C
47	FLIM	FLIM Wb, Ws	Force Data (Upper and Lower) Range Limit without Limit Excess Result	1	2	N, Z, OV
		FLIM Wb, Ws, Wd	Force Data (Upper and Lower) Range Limit with Limit Excess Flag (Wd=-1)	1	2	N, Z, OV
		FLIM.V Wb, Ws, Wd	Force Data (Upper and Lower) Range Limit with Limit Excess Result	1	2	N, Z, OV
48	GOTO	GOTO Label	Goto address (address < ~ 16MB)	1	2	None
		GOTO Label	(label < ~ 16MB)	2	2	None
		GOTO Wn	Go to indirect address at [W11]	1	2	None
49	INC	INC f	f = f + 1	1	1	C, N, OV, Z
		INC f,Wd	W5 = f + 1	1	1	C, N, OV, Z
		INC Ws,Wd	Wd = Ws + 1	1	1	C, N, OV, Z
50	INC2	INC2 f	f = f + 2	1	1	C, N, OV, Z
		INC2 f,Wd	W5 = f + 2	1	1	C, N, OV, Z
		INC2 Ws,Wd	Wd = Ws +2	1	1	C, N, OV, Z
51	IOR	IOR f,Wn	f = f .IOR. Wn	1	1	N, Z
		IOR f,Wn,Wn	Wn = f .IOR. Wn	1	1	N, Z
		IOR #lit16,Wn	Wn = Wn .IOR. lit16	1	1	N, Z
		IOR Wb,Ws,Wd	Wd = Wb .IOR. Ws	0.5/1	1	N, Z
		IOR Wb,#lit7,Wd	Wd = Wb .IOR. lit7	1	1	N, Z
52	LAC	LAC Rso,#Slit6, A	Load Accumulator (16/32-bit), literal shift	1	1	OA, SA, OB, SB
	LLAC	LLAC.l Rso,#Slit6, A	Load Lower (LSw) of Accumulator (32-bit), literal shift	1	1	OA, SA, OB, SB
	LAUC	LUAC.l Rso,#Slit6, A	Load Upper (LSb) of Accumulator (32-bit), literal shift	1	1	OA, SA, OB, SB
53	LNK	LNK #lit16	Link frame pointer	1	1	None
53	LNK	LNK #lit7	Link frame pointer (literal < 128)	0.5	1	None
54	LSR	LSR f	f = Logical Right Shift f by 1	1	1	C,N,Z
		LSR f,Wd	Wd = Logical Right Shift f by 1	1	1	C,N,Z
		LSR Ws,Wd	Wd = Logical Right Shift Ws by 1	0.5/1	1	C,N,Z
		LSR Ws,Wb,Wd	Wnd = Logical Right Shift Ws by Wns	0.5/1	1	C,N,Z
		LSR Ws,#lit5,Wd	Wnd = Logical Right Shift Ws by lit5	0.5/1	1	N,Z
		LSRM Ws,#lit5, Wnd	Wnd = Logical Right Shift Ws by lit5, then logically OR with next lsw	1	2	N,Z
		LSRM Ws, Wb, Wnd	Wnd = Logical Right Shift Ws by Wb, then logically OR with next lsw	1	2	N,Z
55	MAC	MAC Wxp * Wyp, A, AWB	Multiply and Accumulate	1	1	OA, SA, OB, SB
56	MAX	MAX Wb, Ws	Force Data Maximum Range Limit	1	1	OA, SA, OB, SB
		MAX A	Force Data Maximum Range Limit	0.5	1	N, Z, OV
		MAX.V A, Rdo	Force Data Maximum Range Limit with Result	1	2	N, Z, OV
57	MIN	MIN Wb, Ws	Force Data Minimum Range Limit	1	1	N, Z, OV
		MIN A	Force Data Minimum Range Limit	0.5	1	N, Z, OV
		MIN.V A, Rdo	Force Data Minimum Range Limit with Result	1	2	N, Z, OV
58	MOV	MOV Rso,Rdo	Move Ws to Wd	0.5/1	1	None
		MOV.l #lit32,Wnd	Move 32-bit unsigned literal to Wnd	2	2	None
		MOV.sl #lit24,Wnd	Move 24-bit unsigned literal to Wnd; 0 extend to 32-bits	1	1	None
		MOV.w #lit16,Wnd	Move 16-bit unsigned literal to Wnd; 0 extend to 32-bits	1	1	None
		MOV.bz #lit8,Wnd	Move 8-bit unsigned literal to Wnd; 0 extend to 32-bits	1	1	None
		MOV.l [W15-#lit7], Wnd [W14+#slit7], Wnd	Move from system stack with literal offset to Wnd using SP or FP	0.5	1	None
		MOV.l Wns, [W15-#lit7] Wns, [W14+#slit7]	Move from Wns to system stack with literal off-set using SP or FP	0.5	1	None
		MOV.l f,Wnd	Move f to Wnd (Word or Long Word)(f < ~1MB)	1	1	None
		MOV.w f,Wnd	Move f to Wnd (Word or Long Word)(f > ~1MB)	2	2	None
		MOV.b f,Wnd	Move f to Wnd (Byte)	1	1	None
		MOV.l Wns,f	Move Wns to f (Word or Long Word)(f < ~1MB)	1	1	None
		MOV.w Wns,f	Move Wns to f (Word or Long Word)(f > ~1MB)	2	2	None
		MOV.b Wns,f	Move Wns to f (Byte)	1	1	None
		MOV [Wns+#Slit12],Wnd	Move [Wns+Slit12] to Wnd	1	1	None
		MOV Wns,[Wnd+#Slit12]	Move Wns to [Wnd+Slit12]	1	1	None
		MOVIF.l CC, Wb, Wns, Wd	If SR.Z=1 Move W1 to [W15++] Else Move W2 to [W15++]	1	1	None
		MOVIF.w CC, Wb, Wns, Wd	If SR.Z=1 Move W1 to [W15++] Else Move W2 to [W15++]	1	1	None
		MOVIF.bz CC, Wb, Wns, Wd	If SR.Z=1 Move W1 to [W15++] Else Move W2 to [W15++]	1	1	None
		MOVIF.b CC, Wb, Wns, Wd	If SR.Z=1 Move W1 to [W15++] Else Move W2 to [W15++]	1	1	None
		MOVR.l	Move Ws to Wd with destination Bit Reversed	1	1	None
		MOVR.w	Move Ws to Wd with destination Bit Reversed	1	1	None
		MOVS.l #slit16, Wd	Move signed extended 16-bit literal to Wd	1	1	None
		MOVS.w #slit16, Wd	Move 16-bit literal to Wd; sign extend to 32-bits if register direct mode.	1	1	None
		MOVS.b #slit8, Wnd	Move 8-bit literal to Wd; no extension.	1	1	None
59	MOVPAG		Not supported			N/A
60	MOVSAC		Not supported			N/A
61	MPY	MPY Wxp * Wyp, A, AWB	Multiply Wm by Wn to Accumulator	1	1	OA, SA, OB, SB
62	MPYN	MPYN Wxp * Wyp, A, AWB	(negative)(Multiply Wm by Wn) to Accumulator	1	1	OA, SA, OB, SB
63	MSC	MSC Wxp * Wyp, A, AWB	Multiply and Subtract from Accumulator	1	1	OA, SA, OB, SB
65	MUL	MUL f, Wn	W2 = f * Wn	1	1	None
		MULISS Wb,Ws,A	Integer: Acc(A or B) = signed(Wb) * signed(Ws)	1	1	None
		MULFSS Wb,Ws,A	Fractional: Acc(A or B) = signed(Wb) * signed(Ws)	1	1	None
		MULISU Wb,Ws,A	Integer: Acc(A or B) = signed(Wb) * unsigned(Ws)	1	1	None
		MULFSU Wb,Ws,A	Fractional: Acc(A or B) = signed(Wb) * unsigned(Ws)	1	1	None
		MULIUS Wb,Ws,A	Integer: Acc(A or B) = unsigned(Wb) * signed(Ws)	1	1	None
		MULFUS Wb,Ws,A	Fractional: Acc(A or B) = unsigned(Wb) * signed(Ws)	1	1	None
		MULIUU Wb,Ws,A	Integer: Acc(A or B) = unsigned(Wb) * unsigned(Ws)	1	1	None
		MULFUU Wb,Ws,A	Fractional: Acc(A or B) = unsigned(Wb) * unsigned(Ws)	1	1	None
		MULISS Wb,#slit8,A	Integer: Acc(A or B) = signed(Wb) * signed(slit8)	1	1	None
		MULFSS Wb,#slit8,A	Integer: Acc(A or B) = signed(Wb) * signed(slit8)	1	1	None
		MULISU Wb,#lit8,A	Integer: Acc(A or B) = signed(Wb) * unsigned(lit8)	1	1	None
		MULFSU Wb,#lit8,A	Integer: Acc(A or B) = signed(Wb) * unsigned(lit8)	1	1	None
		MULIUS Wb,#slit8,A	Integer: Acc(A or B) = signed(Wb) * signed(slit8)	1	1	None
		MULFUS Wb,#slit8,A	Integer: Acc(A or B) = signed(Wb) * signed(slit8)	1	1	None
		MULIUU Wb,#lit8,A	Integer: Acc(A or B) = signed(Wb) * unsigned(lit8)	1	1	None
		MULFUU Wb,#lit8,A	Integer: Acc(A or B) = signed(Wb) * unsigned(lit8)	1	1	None
		MULSS Wb,Ws,Wnd	{Wd}=signed(Wb) * signed(Ws)	0.5/1	1	None
		MULSU Wb,Ws,Wnd	{Wd}=signed(Wb) * unsigned(Ws)	0.5/1	1	None
		MULUS Wb,Ws,Wnd	{Wd}=unsigned(Wb) * signed(Ws)	0.5/1	1	None
		MULUU Wb,Ws,Wnd	{Wd}=unsigned(Wb) * unsigned(Ws)	0.5/1	1	None
		MULSU Wb,#lit8,Wnd	{Wd}=signed(Wb) * unsigned(lit8)	1	1	None
		MULUU Wb,#lit8,Wnd	{Wd}=unsigned(Wb) * unsigned(lit8)	1	1	None
		MULSS Wb,#slit8,Wnd	{Wd}=signed(Wb) * signed(slit8)	1	1	None
		MULUS Wb,#slit8,Wnd	{Wd}=unsigned(Wb) * signed(slit8)	1	1	None
66	NEG	NEG A	Negate Accumulator	1	1	OA, SA, OB, SB
		NEG f	f = f +1	1	1	OA, SA, OB, SB
		NEG f,Wd	Wd = f + 1	1	1	OA, SA, OB, SB
		NEG Ws,Wd	Wd = Ws + 1	1	1	OA, SA, OB, SB
67	NEOP	NEOP	None executable NOP (16-bit instruction pad)	0.5	0	None
68	NOP	NOP	No Operation	1	1	None
68	NOP	NOPR	No Operation	1	1	None
69	NORM	NORM A, Rdo	Normalize Accumulator	1	1	N,OV,Z
70	POP	POP f	Pop f from top of stack (TOS)	1	1	None
		POP {[--Ws],} Wnd	Pop Wnd Register from system stack.	0.5	1	None
		POP Fd	Pop Fd Register from system stack.	0.5	1	None
71	PUSH	PUSH f	Push f to top of stack (TOS)	1	1	None
		PUSH Wns, {[Wd++]}	Push Wns Register to system stack	0.5	1	None
		PUSH Fs	Push Fs Register to system stack	0.5	1	None
72	PWRSAV	PWRSAV mode	Go into sleep mode	0.5	2	WDTO, Sleep
	RCALL	RCALL Label	Relative Call	1	1	None
	RCALL	RCALL Wns	Computed Call	1	2	None
73	REPEAT	REPEAT #lit15	Repeat Next Instruction lit15+1 times	1	1	RA (if lit15 > 0)
		REPEAT #lit5	Repeat Next Instruction lit5+1 times	0.5	1	RA (if lit5 > 0)
		REPEAT Wn	Repeat Next Instruction (Wn)+1 times	1	1	RA (if Wn > 0)
74	RESET	RESET	Software Device Reset	1	1	None
75	RETFIE	RETFIE	Return from interrupt enable	1	4	None
76	RETLW lit16,Wn	RETLW #lit16,Wn	Return from Subroutine with literal in Wn	1	3	None
77	RETURN	RETURN	Return from Subroutine	0.5	3	None
78	RLC	RLC f	f = Rotate Left through Carry f	1	1	C, N, Z
		RLC f,Wd	Wd = Rotate Left through Carry f	1	1	C, N, Z
		RLC Ws,Wd	Wd = Rotate Left through Carry Ws	0.5/1	1	C, N, Z
79	RLNC	RLNC f	f = Rotate Left (No Carry) f	1	1	N, Z
		RLNC f,Wd	Wd = Rotate Left (No Carry) f	1	1	N, Z
		RLNC Ws,Wd	Wd = Rotate Left (No Carry) Ws	0.5/1	1	N, Z
80	RRC	RRC f	f = Rotate Right through Carry f	1	1	C, N, Z
		RRC f,Wd	Wd = Rotate Right through Carry f	1	1	C, N, Z
		RRC Ws,Wd	Wd = Rotate Right through Carry Ws	0.5/1	1	C, N, Z
81	RRNC	RRNC f	f = Rotate Right (No Carry) f	1	1	N, Z
		RRNC f,Wd	Wd = Rotate Right (No Carry) f	1	1	N, Z
		RRNC Ws,Wd	Wd = Rotate Right (No Carry) Ws	0.5/1	1	N, Z
82	SAC	SAC A,#Slit6,Rdo	Store Accumulator (16/32-bit)	1	1	None
		SACR A,#Slit6,Rdo	Store Rounded Accumulator (16/32-bit), literal shift	1	1	None
		SACRW A,Ws,Rdo	Store Rounded Accumulator (16/32-bit), Wb shift	1	1	None
83	SE	SE Rso,Wnd	Wd = sign-extended Ws	0.5/1	1	C, N, Z
84	SETM	SETM f	f = 0xFFFF FFFF	1	1	None
84	SETM	SETM Wd	Wd = 0xFFFF FFFF	1	1	None
85	SFTAC	SFTAC A,Wn	Arithmetic Shift by (Wn) Accumulator	1	1	OA, SA, OB, SB
85	SFTAC	SFTAC A,#Slit7	Arithmetic Shift by Slit7 Accumulator	1	1	OA, SA, OB, SB
86	SL	SL f	f = Left Shift f by 1	1	1	C, N, Z
		SL f,Wd	Wd = Left Shift f by 1	1	1	C, N, Z
		SL Ws,Wd	Wd = Left Shift Ws by 1	0.5/1	1	C, N, Z
		SL Ws,Wb,Wnd	Wnd = Left Shift Wb by Wns	0.5/1	1	C, N, Z
		SL Ws,#lit5,Wnd	Wnd = Left Shift Ws by lit5	0.5/1	1	C, N, Z
	SLM	SLM Ws, #lit5, Wnd	Wnd = Left Shift Wb by lit5, then logically OR with next msw	1	2	Z
	SLM	SLM Ws, Wb, Wnd	Wnd = Left Shift Wb by Wb, then logically OR with next msw	1	2	Z
87	SLAC	SLAC.l A,#Slit6,Rdo	Store Lower (lsw of) Accumulator (32-bit), literal shift	1	1	None
88	SUAC	SUAC.l A,#Slit6,Rdo	Store sign extended Upper (MSB) Accumulator (32- bit), literal shift	1	1	None
89	SUB	SUB A	Subtract Accumulators	0.5	1	OA, SA, OB, SB
		SUB Rso,#Slit6, A	16-bit Signed Subtract from Accumulator	1	1	OA, SA, OB, SB
		SUB f,Wn	f = f - Wn	1	1	C, N, OV, Z
		SUB f,Wn,Wn	Wn = f - Wn	1	1	C, N, OV, Z
		SUB.l #lit5,Wn	Wn = Wn - lit5	0.5	1	C, N, OV, Z
		SUB #lit16,Wn	Wn = Wn - lit16	1	1	C, N, OV, Z
		SUB Wb,Ws,Wd	Wd = Wb - Ws	0.5/1	1	C, N, OV, Z
		SUB Ws,#lit7,Wd	Wd = Ws - lit7 (literal zero-extended)	1	1	C, N, OV, Z
90	SUBB	SUBB f,Wn	f = f - Wn - (C)	1	1	C, N, OV, Z
		SUBB f,Wn,Wn	Wn = f - Wn - (C)	1	1	C, N, OV, Z
		SUBB #lit16,Wn	Wn = Wn - lit16 - (C)	1	1	C, N, OV, Z
		SUBB Wb,Ws,Wd	Wd = Wb - Ws - (C)	0.5/1	1	C, N, OV, Z
		SUBB Ws,#lit7,Wd	Wd = Ws - lit7 - (literal zero-extended)	1	1	C, N, OV, Z
91	SUBR	SUBR f,Wn	f = Wn - f	1	1	C, N, OV, Z
		SUBR f,Wn,Wn	Wn = Wn - f	1	1	C, N, OV, Z
		SUBR Wb,Ws,Wd	Wd = Ws - Wb	0.5/1	1	C, N, OV, Z
		SUBR Ws,#lit7,Wd	Wd = lit7 - Ws (literal zero-extended)	0.5/1	1	C, N, OV, Z
92	SUBBR	SUBBR f,Wn	f = Wn - f - (C)	1	1	C, N, OV, Z
		SUBBR f,Wn,Wn	Wn = Wn -f - (C)	1	1	C, N, OV, Z
		SUBBR Wb,Ws,Wd	Wd = Ws - Wb - (C)	0.5/1	1	C, N, OV, Z
		SUBBR Ws,#lit7,Wd	Wd = lit7 - Ws - (C) (literal zero-extended)	1	1	C, N, OV, Z
93	SWAP	SWAP Wn	Wn = Word or byte swap Wn	1	1	None
94	SQR	SQR Wxp, A, AWB	Square to Accumulator	1	1	OA, SA, OB, SB
95	SQRAC	SQRAC Wxp, A, AWB	Square and Accumulate	1	1	OA, SA, OB, SB
96	SQRN	SQRN Wxp, A, AWB	Negated Square to Accumulator	1	1	OA, SA, OB, SB
97	SQRSC	SQRSC Wxp, A, AWB	Square and Subtract from Accumulator	1	1	OA, SA, OB, SB
98	TBLRDH		Not supported			N/A
99	TBLRDL		Not supported			N/A
100	TBLWTH		Not supported			N/A
101	TBLWTL		Not supported			N/A
102	TST	TST f	Test f	1	1	N, Z
102	TST	TST f,Wnd	Test f and move f to Wnd	1	1	N, Z
103	ULNK	ULNK	Unlink frame pointer	1	1	None
104	XOR	XOR f,Wn	f = f .XOR. Wn	1	1	N, Z
		XOR f,Wn,Wn	Wn = f .XOR. Wn	1	1	N, Z
		XOR lit16,Wn	Wn = Wn .XOR. lit16	1	1	N, Z
		XOR Wb,Ws,Wd	Wd = Wb .XOR. Ws	0.5/1	1	N, Z
		XOR Wb,lit7,Wd	Wd = Wb .XOR. Lit7 (literal zero-extended)	1	1	N, Z
105	ZE	ZE Rso,Wnd	Wd = Zero-extend Ws	0.5/1	1	C, N, Z
Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. For PIC32AK1216GC41064 devices, the divide instructions must be preceded with a “`REPEAT #5`” instruction, such that they are executed six consecutive times.