4.4 Throughput Summary of Evaluation Kit

The following tables list the observed throughput values.

Table 4-1. PolarFire Throughput Summary—PCIe Continuous DMA Mode
DMA Transfer TypeDMA SizeThroughput (MBps)Average Throughput (MBps)
PC to LSRAM64K10911069
LSRAM to PC11041147
Both PC to and from LSRAM1124/11541093/1149
PC to DDR464K998970
DDR4 to PC5231523
Both PC to and from DDR4998/523972/523
PC to DDR3L64K704714
DDR3L to PC4251327
Both PC to and from DDR3L708/425727/426
Important:
  1. The PCIe DMA performs maximum of 32 beat AXI burst transactions (not AXI4's maximum of 256 beat), which causes low read performance of DDR3L/DDR4.
Table 4-2. PolarFire Throughput Summary—PCIe SGDMA Mode
DMA Transfer TypeDMA SizeThroughput (MBps)Average Throughput (MBps)
PC to DDR41 MB986984
DDR4 to PC5241524
Both PC to and from DDR4986/524980/524
PC to DDR3L1 MB469472
DDR3L to PC3251325
Both PC to and from DDR3L473/325473/325
Important:
  1. The PCIe DMA performs maximum of 32 beat AXI burst transactions (not maximum of 256 beat of AXI4), which causes low read performance of DDR3L/DDR4.
Table 4-3. PolarFire Throughput Summary—Fabric Core DMA Mode
DMA Transfer TypeDMA SizeThroughput (MBps)Average Throughput (MBps)
LSRAM to DDR41 MB14701470
DDR4 to LSRAM12451245
Both LSRAM to and from DDR41470/12451470/1245
LSRAM to DDR3L1 MB574574
DDR3L to LSRAM553553
Both LSRAM to and from DDR3L574/554574/554
DDR4 to DDR3L1 MB574574
DDR3L to DDR4553553
Both DDR4 to and from DDR3L574/553574/553
Important: DDR3L throughput is less due to the AXI interconnect CDC path limitation.