32.3.3.7.1 Single Conversion

The figure below shows the timing diagram for the ADC when running in Single 8- or 10-bit mode.

Figure 32-3. Timing Diagram - Single Conversion

Note:

In Single 8-bit mode, the length of the Conversion state is nine CLK_ADC cycles. In all other modes, it is thirteen cycles.
If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the analog modules in the ADC will not turn OFF at the end of the conversion, which will eliminate the initialization time when triggering the following conversion.
The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles followed by 1 CLK_MAIN cycle. With minimum prescaling, this sums up to 1 CLK_ADC cycle.

The total conversion time for a single result is calculated by:

t_{c o n v} (10-bit) = t_{i n i t i a l i z a t i o n} + \frac{SAMPDUR + 13}{f_{CLK_ADC}}

t_{c o n v} (8-bit) = t_{i n i t i a l i z a t i o n} + \frac{SAMPDUR + 11}{f_{CLK_ADC}}

If the Free-Running (FREERUN) bit is set to ‘1’ in the Control F (ADCn.CTRLF) register, a new conversion will be started immediately after a result is available in the Result (ADCn.RESULT) register. The Free-Running conversion rate (f_conv) is calculated by:

f_{conv} (10-bit) = \frac{f_{CLK_ADC}}{SAMPDUR + 13}

f_{conv} (8-bit) = \frac{f_{CLK_ADC}}{SAMPDUR + 11}