23.1.4 CLCy Input MUX Select Register

Note: y = 5-8

Name:	CLCySELL
Offset:	0x0F2C, 0xF38, 0xF44, 0xF50


Bit	15	14	13	12	11	10	9	8
		DS4[2:0]				DS3[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
		DS2[2:0]				DS1[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0

Bits 14:12 – DS4[2:0] Data Selection MUX 4 Signal Selection bits

Value	Description
111	MCCP9 auxiliary output
110	SCCP8 auxiliary output
101	CLCINH RP pin
100	CLC2 output
011	SPI1 Input (SDIx)
010	Comparator 3 output
001	CLC 6 output
000	PWM Event A

Bits 10:8 – DS3[2:0] Data Selection MUX 3 Signal Selection bits

Value	Description
111	MCCP9 OC output
110	SCCP8 OC output
101	CLC8 output
100	UART1 RX
011	SPI1 Output (SDOx)
010	Comparator 2 output
001	CLC 5 output
000	CLCING I/O pin

Bits 6:4 – DS2[2:0] Data Selection MUX 2 Signal Selection bits

Value	Description
111	SCCP7 OC output
110	SCCP6 OC output
101	Comparator 6 output
100	Comparator 5 output
011	UART1 TX
010	Comparator 1 output
001	Comparator 4 output
000	CLCINF I/O pin

Bits 2:0 – DS1[2:0] Data Selection MUX 1 Signal Selection bits

Value	Description
111	SCCP7 auxiliary output
110	SCCP6 auxiliary output
101	CLC1 output
100	REFCLKO output
011	INTRC/LPRC clock source
010	CLC 7 output
001	System clock (F_CY)
000	CLCINE I/O pin

DS70005496D

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