18.6.8 APBB Mask
CAUTION: Disabling the different peripherals clocks is not required as each
peripheral clock is automatically switched off when the peripheral is not accessed.
Disabling specific system peripheral clocks (NVMCTRL, HMATRIXHS, APB Bridges...) will
even prevent correct device behavior.
| Name: | APBBMASK |
| Offset: | 0x18 |
| Reset: | 0x00000037 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| USB | HMATRIXHS | NVMCTRL | DSU | IDAU | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 1 | 1 | 1 | 1 |
Bit 5 – USB USB APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the USB is stopped |
| 1 | The APBB clock for the USB is enabled |
Bit 4 – HMATRIXHS HMATRIXHS APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the HMATRIXHS is stopped |
| 1 | The APBB clock for the HMATRIXHS is enabled |
Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the NVMCTRL is stopped |
| 1 | The APBB clock for the NVMCTRL is enabled |
Bit 1 – DSU DSU APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the DSU is stopped |
| 1 | The APBB clock for the DSU is enabled |
Bit 0 – IDAU IDAU APBB Clock Enable
Note: This bit field is only available
for PIC32CM LS00/LS60 and has no effect for
PIC32CM LE00.
| Value | Description |
|---|---|
| 0 | The APBB clock for the IDAU is stopped |
| 1 | The APBB clock for the IDAU is enabled |