38.10.20 Pipe Status Register n
| Name: | PSTATUSn |
| Offset: | 0x0106 + n*0x20 [n=0..7] |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BK1RDY | BK0RDY | PFREEZE | CURBK | DTGL | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – BK1RDY Bank 1 is ready
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
This bank is not used for Control pipe.
| Value | Description |
|---|---|
| 0 | The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not yet fill in. |
| 1 | The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in. |
Bit 6 – BK0RDY Bank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
This bank is the only one used for Control pipe.
| Value | Description |
|---|---|
| 0 | The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is not yet fill in. |
| 1 | The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in. |
Bit 4 – PFREEZE Pipe Freeze
Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit.
Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit.
- When a STALL handshake has been received.
- After a PIPE has been enabled (rising of bit PEN.N).
- When an LPM transaction has completed whatever handshake is returned or the transaction was timed-out.
- When a pipe transfer was completed with a pipe error. See PINTFLAGn register.
When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be properly completed. PFREEZE bit will be read as “1” only when the ongoing transaction will have been completed.
| Value | Description |
|---|---|
| 0 | The Pipe operates in normal operation. |
| 1 | The Pipe is frozen and no additional requests will be sent to the device on this pipe address. |
Bit 2 – CURBK Current Bank
| Value | Description |
|---|---|
| 0 | The bank0 is the bank that will be used in the next single/multi USB packet. |
| 1 | The bank1 is the bank that will be used in the next single/multi USB packet. |
Bit 0 – DTGL Data Toggle Sequence
Writing a one to the bit EPSTATUSCLR.DTGL will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGL will set this bit.
This bit is toggled automatically by hardware after a data transaction.
This bit will reflect the data toggle in regards of the token type (IN/OUT/SETUP).
| Value | Description |
|---|---|
| 0 | The PID of the next expected transaction will be zero: data 0. |
| 1 | The PID of the next expected transaction will be one: data 1. |