38.7 Register Summary - USB Device
This Register Description section is valid if the USB is in Device mode (CTRLA.MODE=0).
Refer to the Registers Description section for more details on register properties and access permissions.
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | MODE | RUNSTDBY | ENABLE | SWRST | ||||
0x01 | Reserved | |||||||||
| 0x02 | SYNCBUSY | 7:0 | ENABLE | SWRST | ||||||
| 0x03 | QOSCTRL | 7:0 | DQOS[1:0] | CQOS[1:0] | ||||||
0x04 ... 0x07 | Reserved | |||||||||
| 0x08 | CTRLB | 15:8 | LPMHDSK[1:0] | GNAK | ||||||
| 7:0 | NREPLY | SPDCONF[1:0] | UPRSM | DETACH | ||||||
| 0x0A | DADD | 7:0 | ADDEN | DADD[6:0] | ||||||
0x0B | Reserved | |||||||||
| 0x0C | STATUS | 7:0 | LINESTATE[1:0] | SPEED[1:0] | ||||||
| 0x0D | FSMSTATUS | 7:0 | FSMSTATE[6:0] | |||||||
0x0E ... 0x0F | Reserved | |||||||||
| 0x10 | FNUM | 15:8 | FNCERR | FNUM[10:5] | ||||||
| 7:0 | FNUM[4:0] | |||||||||
0x12 ... 0x13 | Reserved | |||||||||
| 0x14 | INTENCLR | 15:8 | LPMSUSP | LPMNYET | ||||||
| 7:0 | RAMACER | UPRSM | EORSM | WAKEUP | EORST | SOF | SUSPEND | |||
0x16 ... 0x17 | Reserved | |||||||||
| 0x18 | INTENSET | 15:8 | LPMSUSP | LPMNYET | ||||||
| 7:0 | RAMACER | UPRSM | EORSM | WAKEUP | EORST | SOF | SUSPEND | |||
0x1A ... 0x1B | Reserved | |||||||||
| 0x1C | INTFLAG | 15:8 | LPMSUSP | LPMNYET | ||||||
| 7:0 | RAMACER | UPRSM | EORSM | WAKEUP | EORST | SOF | SUSPEND | |||
0x1E ... 0x1F | Reserved | |||||||||
| 0x20 | EPINTSMRY | 15:8 | ||||||||
| 7:0 | EPINT7 | EPINT6 | EPINT5 | EPINT4 | EPINT3 | EPINT2 | EPINT1 | EPINT0 | ||
0x22 ... 0x23 | Reserved | |||||||||
| 0x24 | DESCADD | 31:24 | DESCADD[31:24] | |||||||
| 23:16 | DESCADD[23:16] | |||||||||
| 15:8 | DESCADD[15:8] | |||||||||
| 7:0 | DESCADD[7:0] | |||||||||
| 0x28 | PADCAL | 15:8 | TRIM[2:0] | TRANSN[4:2] | ||||||
| 7:0 | TRANSN[1:0] | TRANSP[4:0] | ||||||||
0x2A ... 0xFF | Reserved | |||||||||
| 0x0100 | EPCFG0 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0101 ... 0x0103 | Reserved | |||||||||
| 0x0104 | EPSTATUSCLR0 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0105 | EPSTATUSSET0 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0106 | EPSTATUS0 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0107 | EPINTFLAG0 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0108 | EPINTENCLR0 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0109 | EPINTENSET0 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x010A ... 0x011F | Reserved | |||||||||
| 0x0120 | EPCFG1 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0121 ... 0x0123 | Reserved | |||||||||
| 0x0124 | EPSTATUSCLR1 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0125 | EPSTATUSSET1 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0126 | EPSTATUS1 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0127 | EPINTFLAG1 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0128 | EPINTENCLR1 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0129 | EPINTENSET1 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x012A ... 0x013F | Reserved | |||||||||
| 0x0140 | EPCFG2 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0141 ... 0x0143 | Reserved | |||||||||
| 0x0144 | EPSTATUSCLR2 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0145 | EPSTATUSSET2 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0146 | EPSTATUS2 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0147 | EPINTFLAG2 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0148 | EPINTENCLR2 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0149 | EPINTENSET2 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x014A ... 0x015F | Reserved | |||||||||
| 0x0160 | EPCFG3 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0161 ... 0x0163 | Reserved | |||||||||
| 0x0164 | EPSTATUSCLR3 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0165 | EPSTATUSSET3 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0166 | EPSTATUS3 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0167 | EPINTFLAG3 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0168 | EPINTENCLR3 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0169 | EPINTENSET3 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x016A ... 0x017F | Reserved | |||||||||
| 0x0180 | EPCFG4 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0181 ... 0x0183 | Reserved | |||||||||
| 0x0184 | EPSTATUSCLR4 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0185 | EPSTATUSSET4 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0186 | EPSTATUS4 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0187 | EPINTFLAG4 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0188 | EPINTENCLR4 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0189 | EPINTENSET4 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x018A ... 0x019F | Reserved | |||||||||
| 0x01A0 | EPCFG5 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x01A1 ... 0x01A3 | Reserved | |||||||||
| 0x01A4 | EPSTATUSCLR5 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01A5 | EPSTATUSSET5 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01A6 | EPSTATUS5 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01A7 | EPINTFLAG5 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01A8 | EPINTENCLR5 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01A9 | EPINTENSET5 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x01AA ... 0x01BF | Reserved | |||||||||
| 0x01C0 | EPCFG6 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x01C1 ... 0x01C3 | Reserved | |||||||||
| 0x01C4 | EPSTATUSCLR6 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01C5 | EPSTATUSSET6 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01C6 | EPSTATUS6 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01C7 | EPINTFLAG6 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01C8 | EPINTENCLR6 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01C9 | EPINTENSET6 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x01CA ... 0x01DF | Reserved | |||||||||
| 0x01E0 | EPCFG7 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x01E1 ... 0x01E3 | Reserved | |||||||||
| 0x01E4 | EPSTATUSCLR7 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01E5 | EPSTATUSSET7 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01E6 | EPSTATUS7 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01E7 | EPINTFLAG7 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01E8 | EPINTENCLR7 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01E9 | EPINTENSET7 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |