51.7.52 ISC DMA Control Register
Name: | ISC_DCTRL |
Offset: | 0x3E4 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DONE | FIELD | WB | IE | DVIEW[1:0] | DE | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DONE Descriptor Processing Status
This bit appears only in the descriptor located in memory and can be used only if WB (Write Back) is set.
Value | Description |
---|---|
0 | Descriptor not processed yet. |
1 | Descriptor processed. |
Bit 6 – FIELD Value of Captured Frame Field Signal
This bit is only relevant for interlaced content. It appears only in the descriptor located in memory and can be used only if WB (Write Back) is set.
Value | Description |
---|---|
0 | Field value is 0. |
1 | Field value is 1. |
Bit 5 – WB Write Back Operation Enable
Value | Description |
---|---|
0 | Write Back operation is skipped. |
1 | Write Back operation is performed. |
Bit 4 – IE Interrupt Enable
Value | Description |
---|---|
0 | DMA Done interrupt is generated. |
1 | DMA Done interrupt is not set. |
Bits 2:1 – DVIEW[1:0] Descriptor View
Value | Name | Description |
---|---|---|
0 | PACKED | Packed frame buffer (see ISC_DCTRL.DVIEW = 0) |
1 | SEMIPLANAR | Semi planar frame buffer (see ISC_DCTRL.DVIEW = 1) |
2 | PLANAR | Planar frame buffer (see ISC_DCTRL.DVIEW = 2) |
3 | – | Reserved |
4 | PACKED ADVANCED | Packed frame buffer, metadata channel and timestamp (see ISC_DCTRL.DVIEW = 4) |
5 | SEMIPLANAR ADVANCED | Semi planar frame buffer, metadata channel and timestamp (see ISC_DCTRL.DVIEW = 5) |
6 | PLANAR ADVANCED | Planar frame buffer, metadata channel and timestamp (see ISC_DCTRL.DVIEW = 6) |
Bit 0 – DE Descriptor Enable
Value | Description |
---|---|
0 | Descriptor disabled. |
1 | Descriptor enabled. |